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git01.mediatek.com / filogic / uboot / 6e366caf99a6d1e2e29085bf4d1ba49b29cdc001 / . / configs / M54418TWR_serial_rmii_defconfig
blob: 18e7fe931764168adff37dd4c70dca6dc4a7831b [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1CONFIG_M68K=y
Masahiro Yamada39e48a52015-12-11 12:22:24 +0900[diff] [blame]2CONFIG_SYS_TEXT_BASE=0x47E00000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]3CONFIG_ENV_SIZE=0x2000
4CONFIG_ENV_OFFSET=0x40000
5CONFIG_ENV_SECT_SIZE=0x10000
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]6CONFIG_TARGET_M54418TWR=y
Masahiro Yamada39e48a52015-12-11 12:22:24 +0900[diff] [blame]7CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]8CONFIG_USE_BOOTARGS=y
9CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]10# CONFIG_DISPLAY_BOARDINFO is not set
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]11CONFIG_HUSH_PARSER=y
Adam Ford58dbf862018-02-06 07:58:59 -0600[diff] [blame]12# CONFIG_CMDLINE_EDITING is not set
13# CONFIG_AUTO_COMPLETE is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]14CONFIG_SYS_PROMPT="-> "
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]15# CONFIG_CMD_LOADB is not set
16# CONFIG_CMD_LOADS is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]17CONFIG_CMD_SF=y
18CONFIG_CMD_SPI=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]19# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]20CONFIG_CMD_DHCP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]21CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]22CONFIG_CMD_PING=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]23CONFIG_CMD_CACHE=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]24CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]25CONFIG_ENV_IS_IN_SPI_FLASH=y
Patrick Delaunayf8e932e2019-02-27 15:20:38 +0100[diff] [blame]26CONFIG_USE_ENV_SPI_CS=y
27CONFIG_ENV_SPI_CS=1
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]28CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]29CONFIG_SPI_FLASH=y
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]30CONFIG_SPI_FLASH_ATMEL=y
Angelo Durgehello6e366ca2019-11-15 23:54:14 +0100[diff] [blame^]31CONFIG_DM_ETH=y
32CONFIG_MCFFEC=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]33CONFIG_MII=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]34CONFIG_SPI=y
Angelo Dureghello7a8be6d2019-03-13 21:46:48 +0100[diff] [blame]35CONFIG_DM_SPI=y
Tuomas Tynkkynen4afde862018-02-07 02:42:23 +0200[diff] [blame]36CONFIG_CF_SPI=y