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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Andre Przywarae776fd22013-09-19 18:06:40 +02002/*
Andre Przywara8de142c2013-09-19 18:06:45 +02003 * code for switching cores into non-secure state and into HYP mode
Andre Przywarae776fd22013-09-19 18:06:40 +02004 *
5 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
Andre Przywarae776fd22013-09-19 18:06:40 +02006 */
7
8#include <config.h>
Andre Przywaradd5e8da2013-09-19 18:06:41 +02009#include <linux/linkage.h>
10#include <asm/gic.h>
11#include <asm/armv7.h>
Marc Zyngier855ca662014-07-12 14:24:03 +010012#include <asm/proc-armv/ptrace.h>
Andre Przywaradd5e8da2013-09-19 18:06:41 +020013
14.arch_extension sec
Andre Przywara8de142c2013-09-19 18:06:45 +020015.arch_extension virt
Andre Przywarae776fd22013-09-19 18:06:40 +020016
Marc Zyngier855ca662014-07-12 14:24:03 +010017 .pushsection ._secure.text, "ax"
18
Masahiro Yamada92bd4ac2013-10-07 11:46:56 +090019 .align 5
Andre Przywara8de142c2013-09-19 18:06:45 +020020/* the vector table for secure state and HYP mode */
Andre Przywarae776fd22013-09-19 18:06:40 +020021_monitor_vectors:
22 .word 0 /* reset */
23 .word 0 /* undef */
24 adr pc, _secure_monitor
25 .word 0
26 .word 0
Marc Zyngier855ca662014-07-12 14:24:03 +010027 .word 0
Andre Przywarae776fd22013-09-19 18:06:40 +020028 .word 0
29 .word 0
Andre Przywarae776fd22013-09-19 18:06:40 +020030
Marc Zyngier855ca662014-07-12 14:24:03 +010031.macro is_cpu_virt_capable tmp
32 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
33 and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
34 cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
35.endm
36
Andre Przywarae776fd22013-09-19 18:06:40 +020037/*
38 * secure monitor handler
Bin Meng75574052016-02-05 19:30:11 -080039 * U-Boot calls this "software interrupt" in start.S
Andre Przywarae776fd22013-09-19 18:06:40 +020040 * This is executed on a "smc" instruction, we use a "smc #0" to switch
41 * to non-secure state.
Marc Zyngier855ca662014-07-12 14:24:03 +010042 * r0, r1, r2: passed to the callee
43 * ip: target PC
Andre Przywarae776fd22013-09-19 18:06:40 +020044 */
Andre Przywarae776fd22013-09-19 18:06:40 +020045_secure_monitor:
Marc Zyngier03a12012014-07-12 14:24:05 +010046#ifdef CONFIG_ARMV7_PSCI
47 ldr r5, =_psci_vectors @ Switch to the next monitor
48 mcr p15, 0, r5, c12, c0, 1
49 isb
50
Chen-Yu Tsai70617c72016-06-19 12:38:31 +080051 @ Obtain a secure stack
52 bl psci_stack_setup
53
54 @ Configure the PSCI backend
55 push {r0, r1, r2, ip}
Marc Zyngier03a12012014-07-12 14:24:05 +010056 bl psci_arch_init
Chen-Yu Tsai70617c72016-06-19 12:38:31 +080057 pop {r0, r1, r2, ip}
Marc Zyngier03a12012014-07-12 14:24:05 +010058#endif
59
Ian Campbell363e4242015-09-29 10:27:09 +010060#ifdef CONFIG_ARM_ERRATA_773022
61 mrc p15, 0, r5, c1, c0, 1
62 orr r5, r5, #(1 << 1)
63 mcr p15, 0, r5, c1, c0, 1
64 isb
65#endif
66
67#ifdef CONFIG_ARM_ERRATA_774769
68 mrc p15, 0, r5, c1, c0, 1
69 orr r5, r5, #(1 << 25)
70 mcr p15, 0, r5, c1, c0, 1
71 isb
72#endif
73
Marc Zyngier855ca662014-07-12 14:24:03 +010074 mrc p15, 0, r5, c1, c1, 0 @ read SCR
Marc Zyngier03a12012014-07-12 14:24:05 +010075 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
Marc Zyngier855ca662014-07-12 14:24:03 +010076 orr r5, r5, #0x31 @ enable NS, AW, FW bits
Marc Zyngier03a12012014-07-12 14:24:05 +010077 @ FIQ preserved for secure mode
Marc Zyngier855ca662014-07-12 14:24:03 +010078 mov r6, #SVC_MODE @ default mode is SVC
79 is_cpu_virt_capable r4
Marc Zyngier4cd832b2014-07-12 14:24:00 +010080#ifdef CONFIG_ARMV7_VIRT
Marc Zyngier855ca662014-07-12 14:24:03 +010081 orreq r5, r5, #0x100 @ allow HVC instruction
82 moveq r6, #HYP_MODE @ Enter the kernel as HYP
Andre Przywara8de142c2013-09-19 18:06:45 +020083#endif
84
Marc Zyngier855ca662014-07-12 14:24:03 +010085 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
Marc Zyngiere9195772014-07-12 14:23:59 +010086 isb
Andre Przywarae776fd22013-09-19 18:06:40 +020087
Marc Zyngier4cd832b2014-07-12 14:24:00 +010088 bne 1f
Andre Przywara8de142c2013-09-19 18:06:45 +020089
Marc Zyngier4cd832b2014-07-12 14:24:00 +010090 @ Reset CNTVOFF to 0 before leaving monitor mode
Marc Zyngier855ca662014-07-12 14:24:03 +010091 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
92 ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
93 movne r4, #0
94 mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
Marc Zyngier4cd832b2014-07-12 14:24:00 +0100951:
Marc Zyngier855ca662014-07-12 14:24:03 +010096 mov lr, ip
97 mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
98 tst lr, #1 @ Check for Thumb PC
99 orrne ip, ip, #T_BIT @ Set T if Thumb
100 orr ip, ip, r6 @ Slot target mode in
101 msr spsr_cxfs, ip @ Set full SPSR
102 movs pc, lr @ ERET to non-secure
103
104ENTRY(_do_nonsec_entry)
105 mov ip, r0
106 mov r0, r1
107 mov r1, r2
108 mov r2, r3
109 smc #0
110ENDPROC(_do_nonsec_entry)
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200111
Marc Zyngier855ca662014-07-12 14:24:03 +0100112.macro get_cbar_addr addr
113#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
114 ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
115#else
116 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
117 bfc \addr, #0, #15 @ clear reserved bits
118#endif
119.endm
120
121.macro get_gicd_addr addr
122 get_cbar_addr \addr
123 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
124.endm
Andre Przywara8de142c2013-09-19 18:06:45 +0200125
Marc Zyngier855ca662014-07-12 14:24:03 +0100126.macro get_gicc_addr addr, tmp
127 get_cbar_addr \addr
128 is_cpu_virt_capable \tmp
129 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
130 moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
131 add \addr, \addr, \tmp
132.endm
133
134#ifndef CONFIG_ARMV7_PSCI
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200135/*
Andre Przywaradbbe1962013-09-19 18:06:44 +0200136 * Secondary CPUs start here and call the code for the core specific parts
137 * of the non-secure and HYP mode transition. The GIC distributor specific
138 * code has already been executed by a C function before.
139 * Then they go back to wfi and wait to be woken up by the kernel again.
140 */
141ENTRY(_smp_pen)
Marc Zyngier855ca662014-07-12 14:24:03 +0100142 cpsid i
143 cpsid f
Andre Przywaradbbe1962013-09-19 18:06:44 +0200144
145 bl _nonsec_init
Andre Przywaradbbe1962013-09-19 18:06:44 +0200146
147 adr r0, _smp_pen @ do not use this address again
148 b smp_waitloop @ wait for IPIs, board specific
149ENDPROC(_smp_pen)
Marc Zyngier855ca662014-07-12 14:24:03 +0100150#endif
Andre Przywaradbbe1962013-09-19 18:06:44 +0200151
152/*
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200153 * Switch a core to non-secure state.
154 *
155 * 1. initialize the GIC per-core interface
156 * 2. allow coprocessor access in non-secure modes
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200157 *
158 * Called from smp_pen by secondary cores and directly by the BSP.
159 * Do not assume that the stack is available and only use registers
160 * r0-r3 and r12.
161 *
162 * PERIPHBASE is used to get the GIC address. This could be 40 bits long,
163 * though, but we check this in C before calling this function.
164 */
165ENTRY(_nonsec_init)
Marc Zyngier855ca662014-07-12 14:24:03 +0100166 get_gicd_addr r3
167
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200168 mvn r1, #0 @ all bits to 1
169 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
170
Marc Zyngier855ca662014-07-12 14:24:03 +0100171 get_gicc_addr r3, r1
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200172
Marc Zyngier855ca662014-07-12 14:24:03 +0100173 mov r1, #3 @ Enable both groups
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200174 str r1, [r3, #GICC_CTLR] @ and clear all other bits
175 mov r1, #0xff
176 str r1, [r3, #GICC_PMR] @ set priority mask register
177
Marc Zyngier855ca662014-07-12 14:24:03 +0100178 mrc p15, 0, r0, c1, c1, 2
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200179 movw r1, #0x3fff
Marc Zyngier855ca662014-07-12 14:24:03 +0100180 movt r1, #0x0004
181 orr r0, r0, r1
182 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200183
184/* The CNTFRQ register of the generic timer needs to be
185 * programmed in secure state. Some primary bootloaders / firmware
186 * omit this, so if the frequency is provided in the configuration,
187 * we do this here instead.
188 * But first check if we have the generic timer.
189 */
Andre Przywara70c78932017-02-16 01:20:19 +0000190#ifdef COUNTER_FREQUENCY
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200191 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
192 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
193 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
Andre Przywara70c78932017-02-16 01:20:19 +0000194 ldreq r1, =COUNTER_FREQUENCY
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200195 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
196#endif
197
198 adr r1, _monitor_vectors
199 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200200 isb
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200201
202 mov r0, r3 @ return GICC address
Andre Przywaradd5e8da2013-09-19 18:06:41 +0200203 bx lr
204ENDPROC(_nonsec_init)
Andre Przywaradbbe1962013-09-19 18:06:44 +0200205
206#ifdef CONFIG_SMP_PEN_ADDR
207/* void __weak smp_waitloop(unsigned previous_address); */
208ENTRY(smp_waitloop)
209 wfi
210 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
211 ldr r1, [r1]
Xiubo Li9d946422014-11-21 17:40:54 +0800212#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
213 rev r1, r1
214#endif
Andre Przywaradbbe1962013-09-19 18:06:44 +0200215 cmp r0, r1 @ make sure we dont execute this code
216 beq smp_waitloop @ again (due to a spurious wakeup)
Marc Zyngier855ca662014-07-12 14:24:03 +0100217 mov r0, r1
218 b _do_nonsec_entry
Andre Przywaradbbe1962013-09-19 18:06:44 +0200219ENDPROC(smp_waitloop)
220.weak smp_waitloop
221#endif
Andre Przywara8de142c2013-09-19 18:06:45 +0200222
Marc Zyngier855ca662014-07-12 14:24:03 +0100223 .popsection