| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Stefan Roese | ae6223d | 2015-01-19 11:33:40 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) Marvell International Ltd. and its affiliates |
| Stefan Roese | ae6223d | 2015-01-19 11:33:40 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __XOR_REGS_H |
| 7 | #define __XOR_REGS_H |
| 8 | |
| 9 | /* |
| 10 | * For controllers that have two XOR units, then chans 2 & 3 will be mapped |
| 11 | * to channels 0 & 1 of unit 1 |
| 12 | */ |
| 13 | #define XOR_UNIT(chan) ((chan) >> 1) |
| 14 | #define XOR_CHAN(chan) ((chan) & 1) |
| 15 | |
| 16 | #define MV_XOR_REGS_OFFSET(unit) (0x60900) |
| 17 | #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) |
| 18 | |
| 19 | /* XOR Engine Control Register Map */ |
| 20 | #define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit)) |
| 21 | #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4))) |
| 22 | #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4))) |
| 23 | |
| 24 | /* XOR Engine Interrupt Register Map */ |
| 25 | #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30) |
| 26 | #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40) |
| 27 | #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50) |
| 28 | #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60) |
| 29 | |
| 30 | /* XOR Engine Descriptor Register Map */ |
| 31 | #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4))) |
| 32 | #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4))) |
| 33 | #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4))) |
| 34 | |
| 35 | #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4))) |
| 36 | #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4))) |
| 37 | #define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D0) |
| 38 | #define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D4) |
| 39 | #define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D8) |
| 40 | #define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E0) |
| 41 | #define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E4) |
| 42 | |
| 43 | /* XOR register fileds */ |
| 44 | |
| 45 | /* XOR Engine [0..1] Configuration Registers (XExCR) */ |
| 46 | #define XEXCR_OPERATION_MODE_OFFS (0) |
| 47 | #define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS) |
| 48 | #define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS) |
| 49 | #define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS) |
| 50 | #define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS) |
| 51 | #define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS) |
| 52 | #define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS) |
| 53 | |
| 54 | #define XEXCR_SRC_BURST_LIMIT_OFFS (4) |
| 55 | #define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS) |
| 56 | #define XEXCR_DST_BURST_LIMIT_OFFS (8) |
| 57 | #define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS) |
| 58 | #define XEXCR_DRD_RES_SWP_OFFS (12) |
| 59 | #define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS) |
| 60 | #define XEXCR_DWR_REQ_SWP_OFFS (13) |
| 61 | #define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS) |
| 62 | #define XEXCR_DES_SWP_OFFS (14) |
| 63 | #define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS) |
| 64 | #define XEXCR_REG_ACC_PROTECT_OFFS (15) |
| 65 | #define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS) |
| 66 | |
| 67 | /* XOR Engine [0..1] Activation Registers (XExACTR) */ |
| 68 | #define XEXACTR_XESTART_OFFS (0) |
| 69 | #define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS) |
| 70 | #define XEXACTR_XESTOP_OFFS (1) |
| 71 | #define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS) |
| 72 | #define XEXACTR_XEPAUSE_OFFS (2) |
| 73 | #define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS) |
| 74 | #define XEXACTR_XERESTART_OFFS (3) |
| 75 | #define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS) |
| 76 | #define XEXACTR_XESTATUS_OFFS (4) |
| 77 | #define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS) |
| 78 | #define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS) |
| 79 | #define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS) |
| 80 | #define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS) |
| 81 | |
| 82 | /* XOR Engine [0..1] Destination Pointer Register (XExDPR0) */ |
| 83 | #define XEXDPR_DST_PTR_OFFS (0) |
| 84 | #define XEXDPR_DST_PTR_MASK (0xFFFFFFFF << XEXDPR_DST_PTR_OFFS) |
| 85 | #define XEXDPR_DST_PTR_XOR_MASK (0x3F) |
| 86 | #define XEXDPR_DST_PTR_DMA_MASK (0x1F) |
| 87 | #define XEXDPR_DST_PTR_CRC_MASK (0x1F) |
| 88 | |
| 89 | /* XOR Engine[0..1] Block Size Registers (XExBSR) */ |
| 90 | #define XEXBSR_BLOCK_SIZE_OFFS (0) |
| 91 | #define XEXBSR_BLOCK_SIZE_MASK (0xFFFFFFFF << XEXBSR_BLOCK_SIZE_OFFS) |
| 92 | #define XEXBSR_BLOCK_SIZE_MIN_VALUE (128) |
| 93 | #define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xFFFFFFFF) |
| 94 | |
| 95 | /* XOR Engine Address Decoding Register Map */ |
| 96 | #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4))) |
| 97 | #define XOR_BASE_ADDR_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x250 + ((win) * 4))) |
| 98 | #define XOR_SIZE_MASK_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x270 + ((win) * 4))) |
| 99 | #define XOR_HIGH_ADDR_REMAP_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x290 + ((win) * 4))) |
| 100 | #define XOR_ADDR_OVRD_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x2A0 + ((win) * 4))) |
| 101 | |
| 102 | #endif /* __XOR_REGS_H */ |