| Sonic Zhang | 02bab34 | 2008-11-26 22:16:45 -0500 | [diff] [blame] | 1 | /* |
| 2 | * ATAPI Masks |
| 3 | */ |
| 4 | |
| 5 | #ifndef __BFIN_PERIPHERAL_PATA__ |
| 6 | #define __BFIN_PERIPHERAL_PATA__ |
| 7 | |
| 8 | /* Bit masks for ATAPI_CONTROL */ |
| 9 | #define PIO_START 0x1 /* Start PIO/Reg Op */ |
| 10 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ |
| 11 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ |
| 12 | #define XFER_DIR 0x8 /* Transfer Direction */ |
| 13 | #define IORDY_EN 0x10 /* IORDY Enable */ |
| 14 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ |
| 15 | #define SOFT_RST 0x40 /* Soft Reset */ |
| 16 | #define DEV_RST 0x80 /* Device Reset */ |
| 17 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ |
| 18 | #define END_ON_TERM 0x200 /* End/Terminate Select */ |
| 19 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ |
| 20 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ |
| 21 | |
| 22 | /* Bit masks for ATAPI_STATUS */ |
| 23 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ |
| 24 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ |
| 25 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ |
| 26 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ |
| 27 | |
| 28 | /* Bit masks for ATAPI_DEV_ADDR */ |
| 29 | #define DEV_ADDR 0x1f /* Device Address */ |
| 30 | |
| 31 | /* Bit masks for ATAPI_INT_MASK */ |
| 32 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ |
| 33 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ |
| 34 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ |
| 35 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ |
| 36 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ |
| 37 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ |
| 38 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ |
| 39 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ |
| 40 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ |
| 41 | |
| 42 | /* Bit masks for ATAPI_INT_STATUS */ |
| 43 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ |
| 44 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ |
| 45 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ |
| 46 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ |
| 47 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ |
| 48 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ |
| 49 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ |
| 50 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ |
| 51 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ |
| 52 | |
| 53 | /* Bit masks for ATAPI_LINE_STATUS */ |
| 54 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ |
| 55 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ |
| 56 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ |
| 57 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ |
| 58 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ |
| 59 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ |
| 60 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ |
| 61 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ |
| 62 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ |
| 63 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ |
| 64 | |
| 65 | /* Bit masks for ATAPI_SM_STATE */ |
| 66 | #define PIO_CSTATE 0xf /* PIO mode state machine current state */ |
| 67 | #define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ |
| 68 | #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ |
| 69 | #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ |
| 70 | |
| 71 | /* Bit masks for ATAPI_TERMINATE */ |
| 72 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ |
| 73 | |
| 74 | /* Bit masks for ATAPI_REG_TIM_0 */ |
| 75 | #define T2_REG 0xff /* End of cycle time for register access transfers */ |
| 76 | #define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ |
| 77 | |
| 78 | /* Bit masks for ATAPI_PIO_TIM_0 */ |
| 79 | #define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ |
| 80 | #define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ |
| 81 | #define T4_REG 0xf000 /* DIOW data hold */ |
| 82 | |
| 83 | /* Bit masks for ATAPI_PIO_TIM_1 */ |
| 84 | #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ |
| 85 | |
| 86 | /* Bit masks for ATAPI_MULTI_TIM_0 */ |
| 87 | #define TD 0xff /* DIOR/DIOW asserted pulsewidth */ |
| 88 | #define TM 0xff00 /* Time from address valid to DIOR/DIOW */ |
| 89 | |
| 90 | /* Bit masks for ATAPI_MULTI_TIM_1 */ |
| 91 | #define TKW 0xff /* Selects DIOW negated pulsewidth */ |
| 92 | #define TKR 0xff00 /* Selects DIOR negated pulsewidth */ |
| 93 | |
| 94 | /* Bit masks for ATAPI_MULTI_TIM_2 */ |
| 95 | #define TH 0xff /* Selects DIOW data hold */ |
| 96 | #define TEOC 0xff00 /* Selects end of cycle for DMA */ |
| 97 | |
| 98 | /* Bit masks for ATAPI_ULTRA_TIM_0 */ |
| 99 | #define TACK 0xff /* Selects setup and hold times for TACK */ |
| 100 | #define TENV 0xff00 /* Selects envelope time */ |
| 101 | |
| 102 | /* Bit masks for ATAPI_ULTRA_TIM_1 */ |
| 103 | #define TDVS 0xff /* Selects data valid setup time */ |
| 104 | #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ |
| 105 | |
| 106 | /* Bit masks for ATAPI_ULTRA_TIM_2 */ |
| 107 | #define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ |
| 108 | #define TMLI 0xff00 /* Selects interlock time */ |
| 109 | |
| 110 | /* Bit masks for ATAPI_ULTRA_TIM_3 */ |
| 111 | #define TZAH 0xff /* Selects minimum delay required for output */ |
| 112 | #define READY_PAUSE 0xff00 /* Selects ready to pause */ |
| 113 | |
| 114 | /* Bit masks for ATAPI_CONTROL */ |
| 115 | #define PIO_START 0x1 /* Start PIO/Reg Op */ |
| 116 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ |
| 117 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ |
| 118 | #define XFER_DIR 0x8 /* Transfer Direction */ |
| 119 | #define IORDY_EN 0x10 /* IORDY Enable */ |
| 120 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ |
| 121 | #define SOFT_RST 0x40 /* Soft Reset */ |
| 122 | #define DEV_RST 0x80 /* Device Reset */ |
| 123 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ |
| 124 | #define END_ON_TERM 0x200 /* End/Terminate Select */ |
| 125 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ |
| 126 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ |
| 127 | |
| 128 | /* Bit masks for ATAPI_STATUS */ |
| 129 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ |
| 130 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ |
| 131 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ |
| 132 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ |
| 133 | |
| 134 | /* Bit masks for ATAPI_DEV_ADDR */ |
| 135 | #define DEV_ADDR 0x1f /* Device Address */ |
| 136 | |
| 137 | /* Bit masks for ATAPI_INT_MASK */ |
| 138 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ |
| 139 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ |
| 140 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ |
| 141 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ |
| 142 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ |
| 143 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ |
| 144 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ |
| 145 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ |
| 146 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ |
| 147 | |
| 148 | /* Bit masks for ATAPI_INT_STATUS */ |
| 149 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ |
| 150 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ |
| 151 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ |
| 152 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ |
| 153 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ |
| 154 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ |
| 155 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ |
| 156 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ |
| 157 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ |
| 158 | |
| 159 | /* Bit masks for ATAPI_LINE_STATUS */ |
| 160 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ |
| 161 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ |
| 162 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ |
| 163 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ |
| 164 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ |
| 165 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ |
| 166 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ |
| 167 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ |
| 168 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ |
| 169 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ |
| 170 | |
| 171 | /* Bit masks for ATAPI_SM_STATE */ |
| 172 | #define PIO_CSTATE 0xf /* PIO mode state machine current state */ |
| 173 | #define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ |
| 174 | #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ |
| 175 | #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ |
| 176 | |
| 177 | /* Bit masks for ATAPI_TERMINATE */ |
| 178 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ |
| 179 | |
| 180 | /* Bit masks for ATAPI_REG_TIM_0 */ |
| 181 | #define T2_REG 0xff /* End of cycle time for register access transfers */ |
| 182 | #define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ |
| 183 | |
| 184 | /* Bit masks for ATAPI_PIO_TIM_0 */ |
| 185 | #define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ |
| 186 | #define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ |
| 187 | #define T4_REG 0xf000 /* DIOW data hold */ |
| 188 | |
| 189 | /* Bit masks for ATAPI_PIO_TIM_1 */ |
| 190 | #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ |
| 191 | |
| 192 | /* Bit masks for ATAPI_MULTI_TIM_0 */ |
| 193 | #define TD 0xff /* DIOR/DIOW asserted pulsewidth */ |
| 194 | #define TM 0xff00 /* Time from address valid to DIOR/DIOW */ |
| 195 | |
| 196 | /* Bit masks for ATAPI_MULTI_TIM_1 */ |
| 197 | #define TKW 0xff /* Selects DIOW negated pulsewidth */ |
| 198 | #define TKR 0xff00 /* Selects DIOR negated pulsewidth */ |
| 199 | |
| 200 | /* Bit masks for ATAPI_MULTI_TIM_2 */ |
| 201 | #define TH 0xff /* Selects DIOW data hold */ |
| 202 | #define TEOC 0xff00 /* Selects end of cycle for DMA */ |
| 203 | |
| 204 | /* Bit masks for ATAPI_ULTRA_TIM_0 */ |
| 205 | #define TACK 0xff /* Selects setup and hold times for TACK */ |
| 206 | #define TENV 0xff00 /* Selects envelope time */ |
| 207 | |
| 208 | /* Bit masks for ATAPI_ULTRA_TIM_1 */ |
| 209 | #define TDVS 0xff /* Selects data valid setup time */ |
| 210 | #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ |
| 211 | |
| 212 | /* Bit masks for ATAPI_ULTRA_TIM_2 */ |
| 213 | #define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ |
| 214 | #define TMLI 0xff00 /* Selects interlock time */ |
| 215 | |
| 216 | /* Bit masks for ATAPI_ULTRA_TIM_3 */ |
| 217 | #define TZAH 0xff /* Selects minimum delay required for output */ |
| 218 | #define READY_PAUSE 0xff00 /* Selects ready to pause */ |
| 219 | |
| 220 | #endif /* __BFIN_PERIPHERAL_PATA__ */ |