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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Bin Meng2229c4c2015-05-07 21:34:08 +08002/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng2229c4c2015-05-07 21:34:08 +08004 */
5
6#include <common.h>
Simon Glass1fa70f82019-11-14 12:57:34 -07007#include <cpu_func.h>
Bin Meng5fecada2016-02-01 01:40:56 -08008#include <pci.h>
Miao Yan92106272016-05-22 19:37:17 -07009#include <qfw.h>
Bin Mengef37e7b2015-06-03 09:20:06 +080010#include <asm/irq.h>
Bin Meng2229c4c2015-05-07 21:34:08 +080011#include <asm/post.h>
12#include <asm/processor.h>
Bin Menge456f2b2015-11-06 02:04:49 -080013#include <asm/arch/device.h>
14#include <asm/arch/qemu.h>
15
16static bool i440fx;
17
Miao Yan8a153832016-05-22 19:37:15 -070018#ifdef CONFIG_QFW
19
Miao Yanf3c6a4e2016-05-22 19:37:16 -070020/* on x86, the qfw registers are all IO ports */
Miao Yan8a153832016-05-22 19:37:15 -070021#define FW_CONTROL_PORT 0x510
22#define FW_DATA_PORT 0x511
23#define FW_DMA_PORT_LOW 0x514
24#define FW_DMA_PORT_HIGH 0x518
25
26static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
27 uint32_t size, void *address)
28{
29 uint32_t i = 0;
30 uint8_t *data = address;
31
32 /*
33 * writting FW_CFG_INVALID will cause read operation to resume at
34 * last offset, otherwise read will start at offset 0
Miao Yanf3c6a4e2016-05-22 19:37:16 -070035 *
36 * Note: on platform where the control register is IO port, the
37 * endianness is little endian.
Miao Yan8a153832016-05-22 19:37:15 -070038 */
39 if (entry != FW_CFG_INVALID)
Miao Yanf3c6a4e2016-05-22 19:37:16 -070040 outw(cpu_to_le16(entry), FW_CONTROL_PORT);
41
42 /* the endianness of data register is string-preserving */
Miao Yan8a153832016-05-22 19:37:15 -070043 while (size--)
44 data[i++] = inb(FW_DATA_PORT);
45}
46
47static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
48{
Miao Yanf3c6a4e2016-05-22 19:37:16 -070049 /* the DMA address register is big endian */
Bin Meng95e4a392017-01-18 03:32:56 -080050 outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
Miao Yan8a153832016-05-22 19:37:15 -070051
52 while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
53 __asm__ __volatile__ ("pause");
54}
55
56static struct fw_cfg_arch_ops fwcfg_x86_ops = {
57 .arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
58 .arch_read_dma = qemu_x86_fwcfg_read_entry_dma
59};
60#endif
61
Miao Yan35603ff2016-01-20 01:57:05 -080062static void enable_pm_piix(void)
63{
64 u8 en;
65 u16 cmd;
66
67 /* Set the PM I/O base */
Bin Meng5fecada2016-02-01 01:40:56 -080068 pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
Miao Yan35603ff2016-01-20 01:57:05 -080069
70 /* Enable access to the PM I/O space */
Bin Meng5fecada2016-02-01 01:40:56 -080071 pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
Miao Yan35603ff2016-01-20 01:57:05 -080072 cmd |= PCI_COMMAND_IO;
Bin Meng5fecada2016-02-01 01:40:56 -080073 pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
Miao Yan35603ff2016-01-20 01:57:05 -080074
75 /* PM I/O Space Enable (PMIOSE) */
Bin Meng5fecada2016-02-01 01:40:56 -080076 pci_read_config8(PIIX_PM, PMREGMISC, &en);
Miao Yan35603ff2016-01-20 01:57:05 -080077 en |= PMIOSE;
Bin Meng5fecada2016-02-01 01:40:56 -080078 pci_write_config8(PIIX_PM, PMREGMISC, en);
Miao Yan35603ff2016-01-20 01:57:05 -080079}
80
81static void enable_pm_ich9(void)
82{
83 /* Set the PM I/O base */
Bin Meng5fecada2016-02-01 01:40:56 -080084 pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
Miao Yan35603ff2016-01-20 01:57:05 -080085}
86
Bin Menge456f2b2015-11-06 02:04:49 -080087static void qemu_chipset_init(void)
88{
89 u16 device, xbcs;
90 int pam, i;
91
92 /*
93 * i440FX and Q35 chipset have different PAM register offset, but with
94 * the same bitfield layout. Here we determine the offset based on its
95 * PCI device ID.
96 */
Bin Meng5fecada2016-02-01 01:40:56 -080097 pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
Bin Menge456f2b2015-11-06 02:04:49 -080098 i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
99 pam = i440fx ? I440FX_PAM : Q35_PAM;
100
101 /*
102 * Initialize Programmable Attribute Map (PAM) Registers
103 *
104 * Configure legacy segments C/D/E/F to system RAM
105 */
106 for (i = 0; i < PAM_NUM; i++)
Bin Meng5fecada2016-02-01 01:40:56 -0800107 pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
Bin Menge456f2b2015-11-06 02:04:49 -0800108
109 if (i440fx) {
110 /*
111 * Enable legacy IDE I/O ports decode
112 *
113 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
114 * However Linux ata_piix driver does sanity check on these two
115 * registers to see whether legacy ports decode is turned on.
116 * This is to make Linux ata_piix driver happy.
117 */
Bin Meng5fecada2016-02-01 01:40:56 -0800118 pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
119 pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
Bin Menge456f2b2015-11-06 02:04:49 -0800120
121 /* Enable I/O APIC */
Bin Meng5fecada2016-02-01 01:40:56 -0800122 pci_read_config16(PIIX_ISA, XBCS, &xbcs);
Bin Menge456f2b2015-11-06 02:04:49 -0800123 xbcs |= APIC_EN;
Bin Meng5fecada2016-02-01 01:40:56 -0800124 pci_write_config16(PIIX_ISA, XBCS, xbcs);
Miao Yan35603ff2016-01-20 01:57:05 -0800125
126 enable_pm_piix();
Bin Menge456f2b2015-11-06 02:04:49 -0800127 } else {
128 /* Configure PCIe ECAM base address */
Bin Meng5fecada2016-02-01 01:40:56 -0800129 pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
130 CONFIG_PCIE_ECAM_BASE | BAR_EN);
Miao Yan35603ff2016-01-20 01:57:05 -0800131
132 enable_pm_ich9();
Bin Menge456f2b2015-11-06 02:04:49 -0800133 }
Miao Yan58a3ce22016-01-07 01:32:00 -0800134
Miao Yan4fcd7f22016-05-22 19:37:14 -0700135#ifdef CONFIG_QFW
Miao Yan8a153832016-05-22 19:37:15 -0700136 qemu_fwcfg_init(&fwcfg_x86_ops);
Miao Yan4fcd7f22016-05-22 19:37:14 -0700137#endif
Bin Menge456f2b2015-11-06 02:04:49 -0800138}
Bin Meng2229c4c2015-05-07 21:34:08 +0800139
Bin Meng7172c0a2017-01-18 03:32:55 -0800140#if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
Bin Meng2229c4c2015-05-07 21:34:08 +0800141int arch_cpu_init(void)
142{
Bin Meng2229c4c2015-05-07 21:34:08 +0800143 post_code(POST_CPU_INIT);
Bin Meng2229c4c2015-05-07 21:34:08 +0800144
Masahiro Yamada17103212016-09-06 22:17:36 +0900145 return x86_cpu_init_f();
Bin Meng2229c4c2015-05-07 21:34:08 +0800146}
Simon Glassee7c36f2017-03-28 10:27:30 -0600147
148int checkcpu(void)
149{
150 return 0;
151}
152
Bin Meng2229c4c2015-05-07 21:34:08 +0800153int print_cpuinfo(void)
154{
155 post_code(POST_CPU_INFO);
156 return default_print_cpuinfo();
157}
Simon Glass752f9762015-08-04 12:34:03 -0600158#endif
Bin Meng2229c4c2015-05-07 21:34:08 +0800159
Bin Menge456f2b2015-11-06 02:04:49 -0800160int arch_early_init_r(void)
161{
162 qemu_chipset_init();
163
164 return 0;
165}
166
Bin Menge456f2b2015-11-06 02:04:49 -0800167#ifdef CONFIG_GENERATE_MP_TABLE
168int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
169{
170 u8 irq;
171
172 if (i440fx) {
173 /*
174 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
175 * connected to I/O APIC INTPIN#16-19. Instead they are routed
176 * to an irq number controled by the PIRQ routing register.
177 */
Bin Meng5fecada2016-02-01 01:40:56 -0800178 pci_read_config8(PCI_BDF(bus, dev, func),
179 PCI_INTERRUPT_LINE, &irq);
Bin Menge456f2b2015-11-06 02:04:49 -0800180 } else {
181 /*
182 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
183 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
184 */
185 irq = pirq < 8 ? pirq + 16 : pirq + 12;
186 }
187
188 return irq;
189}
190#endif