| Vipin KUMAR | 7cc4c46 | 2010-01-15 19:15:48 +0530 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <config.h> |
| 25 | |
| 26 | /* |
| 27 | * platform specific initializations are already done in Xloader |
| 28 | * Initializations already done include |
| 29 | * DDR, PLLs, IP's clock enable and reset release etc |
| 30 | */ |
| 31 | .globl lowlevel_init |
| 32 | lowlevel_init: |
| 33 | /* By default, U-Boot switches CPU to low-vector */ |
| 34 | /* Revert this as we work in high vector even in U-Boot */ |
| 35 | mrc p15, 0, r0, c1, c0, 0 |
| 36 | orr r0, r0, #0x00002000 |
| 37 | mcr p15, 0, r0, c1, c0, 0 |
| 38 | mov pc, lr |
| 39 | |
| 40 | /* void setfreq(unsigned int device, unsigned int frequency) */ |
| 41 | .global setfreq |
| 42 | setfreq: |
| 43 | stmfd sp!,{r14} |
| 44 | stmfd sp!,{r0-r12} |
| 45 | |
| 46 | mov r8,sp |
| 47 | ldr sp,SRAM_STACK_V |
| 48 | |
| 49 | /* Saving the function arguements for later use */ |
| 50 | mov r4,r0 |
| 51 | mov r5,r1 |
| 52 | |
| 53 | /* Putting DDR into self refresh */ |
| 54 | ldr r0,DDR_07_V |
| 55 | ldr r1,[r0] |
| 56 | ldr r2,DDR_ACTIVE_V |
| 57 | bic r1, r1, r2 |
| 58 | str r1,[r0] |
| 59 | ldr r0,DDR_57_V |
| 60 | ldr r1,[r0] |
| 61 | ldr r2,CYCLES_MASK_V |
| 62 | bic r1, r1, r2 |
| 63 | ldr r2,REFRESH_CYCLES_V |
| 64 | orr r1, r1, r2, lsl #16 |
| 65 | str r1,[r0] |
| 66 | ldr r0,DDR_07_V |
| 67 | ldr r1,[r0] |
| 68 | ldr r2,SREFRESH_MASK_V |
| 69 | orr r1, r1, r2 |
| 70 | str r1,[r0] |
| 71 | |
| 72 | /* flush pipeline */ |
| 73 | b flush |
| 74 | .align 5 |
| 75 | flush: |
| 76 | /* Delay to ensure self refresh mode */ |
| 77 | ldr r0,SREFRESH_DELAY_V |
| 78 | delay: |
| 79 | sub r0,r0,#1 |
| 80 | cmp r0,#0 |
| 81 | bne delay |
| 82 | |
| 83 | /* Putting system in slow mode */ |
| 84 | ldr r0,SCCTRL_V |
| 85 | mov r1,#2 |
| 86 | str r1,[r0] |
| 87 | |
| 88 | /* Changing PLL(1/2) frequency */ |
| 89 | mov r0,r4 |
| 90 | mov r1,r5 |
| 91 | |
| 92 | cmp r4,#0 |
| 93 | beq pll1_freq |
| 94 | |
| 95 | /* Change PLL2 (DDR frequency) */ |
| 96 | ldr r6,PLL2_FREQ_V |
| 97 | ldr r7,PLL2_CNTL_V |
| 98 | b pll2_freq |
| 99 | |
| 100 | pll1_freq: |
| 101 | /* Change PLL1 (CPU frequency) */ |
| 102 | ldr r6,PLL1_FREQ_V |
| 103 | ldr r7,PLL1_CNTL_V |
| 104 | |
| 105 | pll2_freq: |
| 106 | mov r0,r6 |
| 107 | ldr r1,[r0] |
| 108 | ldr r2,PLLFREQ_MASK_V |
| 109 | bic r1,r1,r2 |
| 110 | mov r2,r5,lsr#1 |
| 111 | orr r1,r1,r2,lsl#24 |
| 112 | str r1,[r0] |
| 113 | |
| 114 | mov r0,r7 |
| 115 | ldr r1,P1C0A_V |
| 116 | str r1,[r0] |
| 117 | ldr r1,P1C0E_V |
| 118 | str r1,[r0] |
| 119 | ldr r1,P1C06_V |
| 120 | str r1,[r0] |
| 121 | ldr r1,P1C0E_V |
| 122 | str r1,[r0] |
| 123 | |
| 124 | lock: |
| 125 | ldr r1,[r0] |
| 126 | and r1,r1,#1 |
| 127 | cmp r1,#0 |
| 128 | beq lock |
| 129 | |
| 130 | /* Putting system back to normal mode */ |
| 131 | ldr r0,SCCTRL_V |
| 132 | mov r1,#4 |
| 133 | str r1,[r0] |
| 134 | |
| 135 | /* Putting DDR back to normal */ |
| 136 | ldr r0,DDR_07_V |
| 137 | ldr r1,[R0] |
| 138 | ldr r2,SREFRESH_MASK_V |
| 139 | bic r1, r1, r2 |
| 140 | str r1,[r0] |
| 141 | ldr r2,DDR_ACTIVE_V |
| 142 | orr r1, r1, r2 |
| 143 | str r1,[r0] |
| 144 | |
| 145 | /* Delay to ensure self refresh mode */ |
| 146 | ldr r0,SREFRESH_DELAY_V |
| 147 | 1: |
| 148 | sub r0,r0,#1 |
| 149 | cmp r0,#0 |
| 150 | bne 1b |
| 151 | |
| 152 | mov sp,r8 |
| 153 | /* Resuming back to code */ |
| 154 | ldmia sp!,{r0-r12} |
| 155 | ldmia sp!,{pc} |
| 156 | |
| 157 | SCCTRL_V: |
| 158 | .word 0xfca00000 |
| 159 | PLL1_FREQ_V: |
| 160 | .word 0xfca8000C |
| 161 | PLL1_CNTL_V: |
| 162 | .word 0xfca80008 |
| 163 | PLL2_FREQ_V: |
| 164 | .word 0xfca80018 |
| 165 | PLL2_CNTL_V: |
| 166 | .word 0xfca80014 |
| 167 | PLLFREQ_MASK_V: |
| 168 | .word 0xff000000 |
| 169 | P1C0A_V: |
| 170 | .word 0x1C0A |
| 171 | P1C0E_V: |
| 172 | .word 0x1C0E |
| 173 | P1C06_V: |
| 174 | .word 0x1C06 |
| 175 | |
| 176 | SREFRESH_DELAY_V: |
| 177 | .word 0x9999 |
| 178 | SRAM_STACK_V: |
| 179 | .word 0xD2800600 |
| 180 | DDR_07_V: |
| 181 | .word 0xfc60001c |
| 182 | DDR_ACTIVE_V: |
| 183 | .word 0x01000000 |
| 184 | DDR_57_V: |
| 185 | .word 0xfc6000e4 |
| 186 | CYCLES_MASK_V: |
| 187 | .word 0xffff0000 |
| 188 | REFRESH_CYCLES_V: |
| 189 | .word 0xf0f0 |
| 190 | SREFRESH_MASK_V: |
| 191 | .word 0x00010000 |
| 192 | |
| 193 | .global setfreq_sz |
| 194 | setfreq_sz: |
| 195 | .word setfreq_sz - setfreq |