blob: ae3213f959d5f2d50d576c92f714f95351c5c8e5 [file] [log] [blame]
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +09001/*
2 * include/configs/blanche.h
3 * This file is blanche board configuration.
4 *
5 * Copyright (C) 2016 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __BLANCHE_H
11#define __BLANCHE_H
12
13#undef DEBUG
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090014#define CONFIG_RMOBILE_BOARD_STRING "Blanche"
15
16#include "rcar-gen2-common.h"
17
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090018/* STACK */
19#define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC
20#define STACK_AREA_SIZE 0xC000
21#define LOW_LEVEL_MERAM_STACK \
22 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
23
24/* MEMORY */
25#define RCAR_GEN2_SDRAM_BASE 0x40000000
26#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
27#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
28
29/* SCIF */
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090030#define CONFIG_CONS_SCIF0
31
32#define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE)
33#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024)
34
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090035#undef CONFIG_SYS_MEMTEST_SCRATCH
36#undef CONFIG_SYS_LOADS_BAUD_CHANGE
37
38/* FLASH */
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090039#if !defined(CONFIG_MTD_NOR_FLASH)
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090040#define CONFIG_SH_QSPI_BASE 0xE6B10000
41#else
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090042#define CONFIG_SYS_FLASH_CFI
43#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
44#define CONFIG_FLASH_CFI_DRIVER
45#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
46#define CONFIG_FLASH_SHOW_PROGRESS 45
47#define CONFIG_SYS_FLASH_BASE 0x00000000
48#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
49#define CONFIG_SYS_MAX_FLASH_SECT 1024
50#define CONFIG_SYS_MAX_FLASH_BANKS 1
51#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
52#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
53
54#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
55#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
56#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
57#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090058#undef CONFIG_CMD_SF
59#undef CONFIG_CMD_SPI
60#endif
61
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090062
63/* Board Clock */
64#define RMOBILE_XTAL_CLK 20000000u
65#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
66#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
67#define CONFIG_SYS_TMU_CLK_DIV 4
68
69/* ENV setting */
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090070#if !defined(CONFIG_MTD_NOR_FLASH)
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090071#else
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090072#undef CONFIG_ENV_ADDR
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090073#define CONFIG_ENV_SECT_SIZE (256 * 1024)
74#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
75#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
76#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
77#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
78#endif
79
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090080/* Module stop status bits */
81/* INTC-RT */
82#define CONFIG_SMSTP0_ENA 0x00400000
83/* SDHI0 */
84#define CONFIG_SMSTP3_ENA 0x00004000
85/* INTC-SYS, IRQC */
86#define CONFIG_SMSTP4_ENA 0x00000180
87/* SCIF0 */
88#define CONFIG_SMSTP7_ENA 0x00200000
89/* QSPI */
90#define CONFIG_SMSTP9_ENA 0x00020000
91/* SYS-DMAC0 */
92#define CONFIG_RMSTP2_ENA 0x00080000
93
94/* SDHI */
95#define CONFIG_SH_SDHI_FREQ 97500000
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090096
97#endif /* __BLANCHE_H */