Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Sascha Hauer, Pengutronix |
| 4 | * |
| 5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. |
| 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 11 | #include <linux/errno.h> |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 12 | #include <asm/io.h> |
| 13 | #include <asm/arch/imx-regs.h> |
| 14 | #include <asm/arch/clock.h> |
| 15 | #include <asm/arch/sys_proto.h> |
Diego Dorta | 3a5bf53 | 2017-09-27 13:12:37 -0300 | [diff] [blame] | 16 | #include <asm/bootm.h> |
Stefano Babic | 33731bc | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 17 | #include <asm/mach-imx/boot_mode.h> |
| 18 | #include <asm/mach-imx/dma.h> |
| 19 | #include <asm/mach-imx/hab.h> |
Fabio Estevam | 48e65b0 | 2013-02-07 06:45:23 +0000 | [diff] [blame] | 20 | #include <stdbool.h> |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 21 | #include <asm/arch/mxc_hdmi.h> |
| 22 | #include <asm/arch/crm_regs.h> |
Ye.Li | f19692c | 2014-11-20 21:14:14 +0800 | [diff] [blame] | 23 | #include <dm.h> |
| 24 | #include <imx_thermal.h> |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 25 | #include <mmc.h> |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 26 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 27 | enum ldo_reg { |
| 28 | LDO_ARM, |
| 29 | LDO_SOC, |
| 30 | LDO_PU, |
| 31 | }; |
| 32 | |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 33 | struct scu_regs { |
| 34 | u32 ctrl; |
| 35 | u32 config; |
| 36 | u32 status; |
| 37 | u32 invalidate; |
| 38 | u32 fpga_rev; |
| 39 | }; |
| 40 | |
Adrian Alonso | ce08c36 | 2015-09-02 13:54:13 -0500 | [diff] [blame] | 41 | #if defined(CONFIG_IMX_THERMAL) |
Ye.Li | f19692c | 2014-11-20 21:14:14 +0800 | [diff] [blame] | 42 | static const struct imx_thermal_plat imx6_thermal_plat = { |
| 43 | .regs = (void *)ANATOP_BASE_ADDR, |
| 44 | .fuse_bank = 1, |
| 45 | .fuse_word = 6, |
| 46 | }; |
| 47 | |
| 48 | U_BOOT_DEVICE(imx6_thermal) = { |
| 49 | .name = "imx_thermal", |
| 50 | .platdata = &imx6_thermal_plat, |
| 51 | }; |
| 52 | #endif |
| 53 | |
Adrian Alonso | 6ec8d84 | 2015-10-12 13:48:12 -0500 | [diff] [blame] | 54 | #if defined(CONFIG_SECURE_BOOT) |
| 55 | struct imx_sec_config_fuse_t const imx_sec_config_fuse = { |
| 56 | .bank = 0, |
| 57 | .word = 6, |
| 58 | }; |
| 59 | #endif |
| 60 | |
Gabriel Huau | 170ceaf | 2014-07-26 11:35:43 -0700 | [diff] [blame] | 61 | u32 get_nr_cpus(void) |
| 62 | { |
| 63 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; |
| 64 | return readl(&scu->config) & 3; |
| 65 | } |
| 66 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 67 | u32 get_cpu_rev(void) |
| 68 | { |
Fabio Estevam | 46e9733 | 2012-03-20 04:21:45 +0000 | [diff] [blame] | 69 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 70 | u32 reg = readl(&anatop->digprog_sololite); |
| 71 | u32 type = ((reg >> 16) & 0xff); |
Peng Fan | 5f24792 | 2015-07-11 11:38:42 +0800 | [diff] [blame] | 72 | u32 major, cfg = 0; |
Fabio Estevam | 46e9733 | 2012-03-20 04:21:45 +0000 | [diff] [blame] | 73 | |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 74 | if (type != MXC_CPU_MX6SL) { |
| 75 | reg = readl(&anatop->digprog); |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 76 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; |
Peng Fan | 5f24792 | 2015-07-11 11:38:42 +0800 | [diff] [blame] | 77 | cfg = readl(&scu->config) & 3; |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 78 | type = ((reg >> 16) & 0xff); |
| 79 | if (type == MXC_CPU_MX6DL) { |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 80 | if (!cfg) |
| 81 | type = MXC_CPU_MX6SOLO; |
| 82 | } |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 83 | |
| 84 | if (type == MXC_CPU_MX6Q) { |
| 85 | if (cfg == 1) |
| 86 | type = MXC_CPU_MX6D; |
| 87 | } |
| 88 | |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 89 | } |
Peng Fan | 8838323 | 2015-06-11 18:30:36 +0800 | [diff] [blame] | 90 | major = ((reg >> 8) & 0xff); |
Peng Fan | 5f24792 | 2015-07-11 11:38:42 +0800 | [diff] [blame] | 91 | if ((major >= 1) && |
| 92 | ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { |
| 93 | major--; |
| 94 | type = MXC_CPU_MX6QP; |
| 95 | if (cfg == 1) |
| 96 | type = MXC_CPU_MX6DP; |
| 97 | } |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 98 | reg &= 0xff; /* mx6 silicon revision */ |
Peng Fan | 8838323 | 2015-06-11 18:30:36 +0800 | [diff] [blame] | 99 | return (type << 12) | (reg + (0x10 * (major + 1))); |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 100 | } |
| 101 | |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 102 | /* |
| 103 | * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440) |
| 104 | * defines a 2-bit SPEED_GRADING |
| 105 | */ |
| 106 | #define OCOTP_CFG3_SPEED_SHIFT 16 |
| 107 | #define OCOTP_CFG3_SPEED_800MHZ 0 |
| 108 | #define OCOTP_CFG3_SPEED_850MHZ 1 |
| 109 | #define OCOTP_CFG3_SPEED_1GHZ 2 |
| 110 | #define OCOTP_CFG3_SPEED_1P2GHZ 3 |
| 111 | |
Peng Fan | 441e905 | 2016-05-03 11:13:04 +0800 | [diff] [blame] | 112 | /* |
| 113 | * For i.MX6UL |
| 114 | */ |
| 115 | #define OCOTP_CFG3_SPEED_528MHZ 1 |
| 116 | #define OCOTP_CFG3_SPEED_696MHZ 2 |
| 117 | |
Sébastien Szymanski | b130c8a | 2017-08-02 17:05:27 +0200 | [diff] [blame] | 118 | /* |
| 119 | * For i.MX6ULL |
| 120 | */ |
| 121 | #define OCOTP_CFG3_SPEED_792MHZ 2 |
| 122 | #define OCOTP_CFG3_SPEED_900MHZ 3 |
| 123 | |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 124 | u32 get_cpu_speed_grade_hz(void) |
| 125 | { |
| 126 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 127 | struct fuse_bank *bank = &ocotp->bank[0]; |
| 128 | struct fuse_bank0_regs *fuse = |
| 129 | (struct fuse_bank0_regs *)bank->fuse_regs; |
| 130 | uint32_t val; |
| 131 | |
| 132 | val = readl(&fuse->cfg3); |
| 133 | val >>= OCOTP_CFG3_SPEED_SHIFT; |
| 134 | val &= 0x3; |
| 135 | |
Sébastien Szymanski | b130c8a | 2017-08-02 17:05:27 +0200 | [diff] [blame] | 136 | if (is_mx6ul()) { |
Peng Fan | 441e905 | 2016-05-03 11:13:04 +0800 | [diff] [blame] | 137 | if (val == OCOTP_CFG3_SPEED_528MHZ) |
| 138 | return 528000000; |
| 139 | else if (val == OCOTP_CFG3_SPEED_696MHZ) |
Sébastien Szymanski | 415c7ce | 2017-08-02 17:05:26 +0200 | [diff] [blame] | 140 | return 696000000; |
Peng Fan | 441e905 | 2016-05-03 11:13:04 +0800 | [diff] [blame] | 141 | else |
| 142 | return 0; |
| 143 | } |
| 144 | |
Sébastien Szymanski | b130c8a | 2017-08-02 17:05:27 +0200 | [diff] [blame] | 145 | if (is_mx6ull()) { |
| 146 | if (val == OCOTP_CFG3_SPEED_528MHZ) |
| 147 | return 528000000; |
| 148 | else if (val == OCOTP_CFG3_SPEED_792MHZ) |
| 149 | return 792000000; |
| 150 | else if (val == OCOTP_CFG3_SPEED_900MHZ) |
| 151 | return 900000000; |
| 152 | else |
| 153 | return 0; |
| 154 | } |
| 155 | |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 156 | switch (val) { |
| 157 | /* Valid for IMX6DQ */ |
| 158 | case OCOTP_CFG3_SPEED_1P2GHZ: |
Peng Fan | 6c4f76f | 2016-05-23 18:35:58 +0800 | [diff] [blame] | 159 | if (is_mx6dq() || is_mx6dqp()) |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 160 | return 1200000000; |
| 161 | /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ |
| 162 | case OCOTP_CFG3_SPEED_1GHZ: |
| 163 | return 996000000; |
| 164 | /* Valid for IMX6DQ */ |
| 165 | case OCOTP_CFG3_SPEED_850MHZ: |
Peng Fan | 6c4f76f | 2016-05-23 18:35:58 +0800 | [diff] [blame] | 166 | if (is_mx6dq() || is_mx6dqp()) |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 167 | return 852000000; |
| 168 | /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ |
| 169 | case OCOTP_CFG3_SPEED_800MHZ: |
| 170 | return 792000000; |
| 171 | } |
| 172 | return 0; |
| 173 | } |
| 174 | |
Tim Harvey | 5e0e193 | 2015-05-18 06:56:45 -0700 | [diff] [blame] | 175 | /* |
| 176 | * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480) |
| 177 | * defines a 2-bit Temperature Grade |
| 178 | * |
Fabio Estevam | a24859c | 2017-06-22 10:50:05 -0300 | [diff] [blame] | 179 | * return temperature grade and min/max temperature in Celsius |
Tim Harvey | 5e0e193 | 2015-05-18 06:56:45 -0700 | [diff] [blame] | 180 | */ |
| 181 | #define OCOTP_MEM0_TEMP_SHIFT 6 |
| 182 | |
| 183 | u32 get_cpu_temp_grade(int *minc, int *maxc) |
| 184 | { |
| 185 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 186 | struct fuse_bank *bank = &ocotp->bank[1]; |
| 187 | struct fuse_bank1_regs *fuse = |
| 188 | (struct fuse_bank1_regs *)bank->fuse_regs; |
| 189 | uint32_t val; |
| 190 | |
| 191 | val = readl(&fuse->mem0); |
| 192 | val >>= OCOTP_MEM0_TEMP_SHIFT; |
| 193 | val &= 0x3; |
| 194 | |
| 195 | if (minc && maxc) { |
| 196 | if (val == TEMP_AUTOMOTIVE) { |
| 197 | *minc = -40; |
| 198 | *maxc = 125; |
| 199 | } else if (val == TEMP_INDUSTRIAL) { |
| 200 | *minc = -40; |
| 201 | *maxc = 105; |
| 202 | } else if (val == TEMP_EXTCOMMERCIAL) { |
| 203 | *minc = -20; |
| 204 | *maxc = 105; |
| 205 | } else { |
| 206 | *minc = 0; |
| 207 | *maxc = 95; |
| 208 | } |
| 209 | } |
| 210 | return val; |
| 211 | } |
| 212 | |
Fabio Estevam | 435998b | 2013-03-27 07:36:55 +0000 | [diff] [blame] | 213 | #ifdef CONFIG_REVISION_TAG |
| 214 | u32 __weak get_board_rev(void) |
| 215 | { |
| 216 | u32 cpurev = get_cpu_rev(); |
| 217 | u32 type = ((cpurev >> 12) & 0xff); |
| 218 | if (type == MXC_CPU_MX6SOLO) |
| 219 | cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); |
| 220 | |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 221 | if (type == MXC_CPU_MX6D) |
| 222 | cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); |
| 223 | |
Fabio Estevam | 435998b | 2013-03-27 07:36:55 +0000 | [diff] [blame] | 224 | return cpurev; |
| 225 | } |
| 226 | #endif |
| 227 | |
Fabio Estevam | cf621ff | 2013-12-26 14:51:31 -0200 | [diff] [blame] | 228 | static void clear_ldo_ramp(void) |
| 229 | { |
| 230 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
| 231 | int reg; |
| 232 | |
| 233 | /* ROM may modify LDO ramp up time according to fuse setting, so in |
| 234 | * order to be in the safe side we neeed to reset these settings to |
| 235 | * match the reset value: 0'b00 |
| 236 | */ |
| 237 | reg = readl(&anatop->ana_misc2); |
| 238 | reg &= ~(0x3f << 24); |
| 239 | writel(reg, &anatop->ana_misc2); |
| 240 | } |
| 241 | |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 242 | /* |
Fabio Estevam | 2e95fe1 | 2014-06-13 01:42:37 -0300 | [diff] [blame] | 243 | * Set the PMU_REG_CORE register |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 244 | * |
Fabio Estevam | 2e95fe1 | 2014-06-13 01:42:37 -0300 | [diff] [blame] | 245 | * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 246 | * Possible values are from 0.725V to 1.450V in steps of |
| 247 | * 0.025V (25mV). |
| 248 | */ |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 249 | static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 250 | { |
| 251 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 252 | u32 val, step, old, reg = readl(&anatop->reg_core); |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 253 | u8 shift; |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 254 | |
Peng Fan | 81224c4 | 2017-08-08 16:21:35 +0800 | [diff] [blame] | 255 | /* No LDO_SOC/PU/ARM */ |
| 256 | if (is_mx6sll()) |
| 257 | return 0; |
| 258 | |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 259 | if (mv < 725) |
| 260 | val = 0x00; /* Power gated off */ |
| 261 | else if (mv > 1450) |
| 262 | val = 0x1F; /* Power FET switched full on. No regulation */ |
| 263 | else |
| 264 | val = (mv - 700) / 25; |
| 265 | |
Fabio Estevam | cf621ff | 2013-12-26 14:51:31 -0200 | [diff] [blame] | 266 | clear_ldo_ramp(); |
| 267 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 268 | switch (ldo) { |
| 269 | case LDO_SOC: |
| 270 | shift = 18; |
| 271 | break; |
| 272 | case LDO_PU: |
| 273 | shift = 9; |
| 274 | break; |
| 275 | case LDO_ARM: |
| 276 | shift = 0; |
| 277 | break; |
| 278 | default: |
| 279 | return -EINVAL; |
| 280 | } |
| 281 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 282 | old = (reg & (0x1F << shift)) >> shift; |
| 283 | step = abs(val - old); |
| 284 | if (step == 0) |
| 285 | return 0; |
| 286 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 287 | reg = (reg & ~(0x1F << shift)) | (val << shift); |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 288 | writel(reg, &anatop->reg_core); |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 289 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 290 | /* |
| 291 | * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per |
| 292 | * step |
| 293 | */ |
| 294 | udelay(3 * step); |
| 295 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 296 | return 0; |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 297 | } |
| 298 | |
Anson Huang | 05a464f | 2014-01-23 14:00:18 +0800 | [diff] [blame] | 299 | static void set_ahb_rate(u32 val) |
| 300 | { |
| 301 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 302 | u32 reg, div; |
| 303 | |
| 304 | div = get_periph_clk() / val - 1; |
| 305 | reg = readl(&mxc_ccm->cbcdr); |
| 306 | |
| 307 | writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | |
| 308 | (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); |
| 309 | } |
| 310 | |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 311 | static void clear_mmdc_ch_mask(void) |
| 312 | { |
| 313 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
Peng Fan | 53f3c9e | 2015-07-11 11:38:43 +0800 | [diff] [blame] | 314 | u32 reg; |
| 315 | reg = readl(&mxc_ccm->ccdr); |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 316 | |
| 317 | /* Clear MMDC channel mask */ |
Peng Fan | 81224c4 | 2017-08-08 16:21:35 +0800 | [diff] [blame] | 318 | if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll()) |
Ye Li | 64cef44 | 2016-03-09 16:13:48 +0800 | [diff] [blame] | 319 | reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); |
| 320 | else |
| 321 | reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); |
Peng Fan | 53f3c9e | 2015-07-11 11:38:43 +0800 | [diff] [blame] | 322 | writel(reg, &mxc_ccm->ccdr); |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 323 | } |
| 324 | |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 325 | #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8 |
| 326 | |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 327 | static void init_bandgap(void) |
| 328 | { |
| 329 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 330 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 331 | struct fuse_bank *bank = &ocotp->bank[1]; |
| 332 | struct fuse_bank1_regs *fuse = |
| 333 | (struct fuse_bank1_regs *)bank->fuse_regs; |
| 334 | uint32_t val; |
| 335 | |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 336 | /* |
| 337 | * Ensure the bandgap has stabilized. |
| 338 | */ |
| 339 | while (!(readl(&anatop->ana_misc0) & 0x80)) |
| 340 | ; |
| 341 | /* |
| 342 | * For best noise performance of the analog blocks using the |
| 343 | * outputs of the bandgap, the reftop_selfbiasoff bit should |
| 344 | * be set. |
| 345 | */ |
| 346 | writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); |
Peng Fan | 6b98935 | 2016-08-11 14:02:50 +0800 | [diff] [blame] | 347 | /* |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 348 | * On i.MX6ULL,we need to set VBGADJ bits according to the |
| 349 | * REFTOP_TRIM[3:0] in fuse table |
| 350 | * 000 - set REFTOP_VBGADJ[2:0] to 3b'110, |
| 351 | * 110 - set REFTOP_VBGADJ[2:0] to 3b'000, |
| 352 | * 001 - set REFTOP_VBGADJ[2:0] to 3b'001, |
| 353 | * 010 - set REFTOP_VBGADJ[2:0] to 3b'010, |
| 354 | * 011 - set REFTOP_VBGADJ[2:0] to 3b'011, |
| 355 | * 100 - set REFTOP_VBGADJ[2:0] to 3b'100, |
| 356 | * 101 - set REFTOP_VBGADJ[2:0] to 3b'101, |
| 357 | * 111 - set REFTOP_VBGADJ[2:0] to 3b'111, |
Peng Fan | 6b98935 | 2016-08-11 14:02:50 +0800 | [diff] [blame] | 358 | */ |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 359 | if (is_mx6ull()) { |
| 360 | val = readl(&fuse->mem0); |
| 361 | val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT; |
| 362 | val &= 0x7; |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 363 | |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 364 | writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, |
| 365 | &anatop->ana_misc0_set); |
| 366 | } |
| 367 | } |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 368 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 369 | int arch_cpu_init(void) |
| 370 | { |
Peng Fan | 946333d | 2017-08-08 16:21:38 +0800 | [diff] [blame] | 371 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 372 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 373 | init_aips(); |
| 374 | |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 375 | /* Need to clear MMDC_CHx_MASK to make warm reset work. */ |
| 376 | clear_mmdc_ch_mask(); |
| 377 | |
Anson Huang | 05a464f | 2014-01-23 14:00:18 +0800 | [diff] [blame] | 378 | /* |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 379 | * Disable self-bias circuit in the analog bandap. |
| 380 | * The self-bias circuit is used by the bandgap during startup. |
| 381 | * This bit should be set after the bandgap has initialized. |
| 382 | */ |
| 383 | init_bandgap(); |
| 384 | |
Peng Fan | ae86e3f | 2016-08-11 14:02:43 +0800 | [diff] [blame] | 385 | if (!is_mx6ul() && !is_mx6ull()) { |
Peng Fan | f60137e | 2016-03-09 16:44:36 +0800 | [diff] [blame] | 386 | /* |
| 387 | * When low freq boot is enabled, ROM will not set AHB |
| 388 | * freq, so we need to ensure AHB freq is 132MHz in such |
| 389 | * scenario. |
| 390 | * |
| 391 | * To i.MX6UL, when power up, default ARM core and |
| 392 | * AHB rate is 396M and 132M. |
| 393 | */ |
| 394 | if (mxc_get_clock(MXC_ARM_CLK) == 396000000) |
| 395 | set_ahb_rate(132000000); |
| 396 | } |
Anson Huang | 05a464f | 2014-01-23 14:00:18 +0800 | [diff] [blame] | 397 | |
Peng Fan | 2b990ea | 2016-09-28 09:40:27 +0800 | [diff] [blame] | 398 | if (is_mx6ul()) { |
| 399 | if (is_soc_rev(CHIP_REV_1_0) == 0) { |
| 400 | /* |
| 401 | * According to the design team's requirement on |
| 402 | * i.MX6UL,the PMIC_STBY_REQ PAD should be configured |
| 403 | * as open drain 100K (0x0000b8a0). |
| 404 | * Only exists on TO1.0 |
| 405 | */ |
| 406 | writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); |
| 407 | } else { |
| 408 | /* |
| 409 | * From TO1.1, SNVS adds internal pull up control |
| 410 | * for POR_B, the register filed is GPBIT[1:0], |
| 411 | * after system boot up, it can be set to 2b'01 |
| 412 | * to disable internal pull up.It can save about |
| 413 | * 30uA power in SNVS mode. |
| 414 | */ |
| 415 | writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & |
| 416 | (~0x1400)) | 0x400, |
| 417 | MX6UL_SNVS_LP_BASE_ADDR + 0x10); |
| 418 | } |
Peng Fan | a2cba65 | 2016-03-09 16:44:37 +0800 | [diff] [blame] | 419 | } |
| 420 | |
Peng Fan | b64bf0b | 2016-08-11 14:02:46 +0800 | [diff] [blame] | 421 | if (is_mx6ull()) { |
| 422 | /* |
| 423 | * GPBIT[1:0] is suggested to set to 2'b11: |
| 424 | * 2'b00 : always PUP100K |
| 425 | * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL |
| 426 | * 2'b10 : always disable PUP100K |
| 427 | * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL |
| 428 | * register offset is different from i.MX6UL, since |
| 429 | * i.MX6UL is fixed by ECO. |
| 430 | */ |
| 431 | writel(readl(MX6UL_SNVS_LP_BASE_ADDR) | |
| 432 | 0x3, MX6UL_SNVS_LP_BASE_ADDR); |
| 433 | } |
| 434 | |
Peng Fan | a2cba65 | 2016-03-09 16:44:37 +0800 | [diff] [blame] | 435 | /* Set perclk to source from OSC 24MHz */ |
Peng Fan | fe7052a | 2017-08-08 16:21:39 +0800 | [diff] [blame] | 436 | if (is_mx6sl()) |
| 437 | setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); |
Ye.Li | 622dfbd | 2014-10-30 18:20:58 +0800 | [diff] [blame] | 438 | |
Fabio Estevam | 5f79d46 | 2017-11-23 10:55:33 -0200 | [diff] [blame] | 439 | imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */ |
Stefan Roese | 8338d1d | 2013-04-15 21:14:12 +0000 | [diff] [blame] | 440 | |
Peng Fan | 946333d | 2017-08-08 16:21:38 +0800 | [diff] [blame] | 441 | if (is_mx6sx()) |
| 442 | setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); |
| 443 | |
Dirk Behme | 0adb215 | 2015-03-09 14:48:48 +0100 | [diff] [blame] | 444 | init_src(); |
| 445 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 446 | return 0; |
| 447 | } |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 448 | |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 449 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 450 | __weak int board_mmc_get_env_dev(int devno) |
| 451 | { |
| 452 | return CONFIG_SYS_MMC_ENV_DEV; |
| 453 | } |
| 454 | |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 455 | static int mmc_get_boot_dev(void) |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 456 | { |
| 457 | struct src *src_regs = (struct src *)SRC_BASE_ADDR; |
| 458 | u32 soc_sbmr = readl(&src_regs->sbmr1); |
| 459 | u32 bootsel; |
| 460 | int devno; |
| 461 | |
| 462 | /* |
| 463 | * Refer to |
| 464 | * "i.MX 6Dual/6Quad Applications Processor Reference Manual" |
| 465 | * Chapter "8.5.3.1 Expansion Device eFUSE Configuration" |
| 466 | * i.MX6SL/SX/UL has same layout. |
| 467 | */ |
| 468 | bootsel = (soc_sbmr & 0x000000FF) >> 6; |
| 469 | |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 470 | /* No boot from sd/mmc */ |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 471 | if (bootsel != 1) |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 472 | return -1; |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 473 | |
| 474 | /* BOOT_CFG2[3] and BOOT_CFG2[4] */ |
| 475 | devno = (soc_sbmr & 0x00001800) >> 11; |
| 476 | |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 477 | return devno; |
| 478 | } |
| 479 | |
| 480 | int mmc_get_env_dev(void) |
| 481 | { |
| 482 | int devno = mmc_get_boot_dev(); |
| 483 | |
| 484 | /* If not boot from sd/mmc, use default value */ |
| 485 | if (devno < 0) |
| 486 | return CONFIG_SYS_MMC_ENV_DEV; |
| 487 | |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 488 | return board_mmc_get_env_dev(devno); |
| 489 | } |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 490 | |
| 491 | #ifdef CONFIG_SYS_MMC_ENV_PART |
| 492 | __weak int board_mmc_get_env_part(int devno) |
| 493 | { |
| 494 | return CONFIG_SYS_MMC_ENV_PART; |
| 495 | } |
| 496 | |
| 497 | uint mmc_get_env_part(struct mmc *mmc) |
| 498 | { |
| 499 | int devno = mmc_get_boot_dev(); |
| 500 | |
| 501 | /* If not boot from sd/mmc, use default value */ |
| 502 | if (devno < 0) |
| 503 | return CONFIG_SYS_MMC_ENV_PART; |
| 504 | |
| 505 | return board_mmc_get_env_part(devno); |
| 506 | } |
| 507 | #endif |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 508 | #endif |
| 509 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 510 | int board_postclk_init(void) |
| 511 | { |
Peng Fan | 81224c4 | 2017-08-08 16:21:35 +0800 | [diff] [blame] | 512 | /* NO LDO SOC on i.MX6SLL */ |
| 513 | if (is_mx6sll()) |
| 514 | return 0; |
| 515 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 516 | set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ |
| 517 | |
| 518 | return 0; |
| 519 | } |
| 520 | |
Anatolij Gustschin | 938734e | 2017-08-28 17:51:33 +0200 | [diff] [blame] | 521 | #ifndef CONFIG_SPL_BUILD |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 522 | /* |
| 523 | * cfg_val will be used for |
| 524 | * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] |
Nikita Kiryanov | 9fba842 | 2014-10-29 19:28:33 +0200 | [diff] [blame] | 525 | * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] |
| 526 | * instead of SBMR1 to determine the boot device. |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 527 | */ |
| 528 | const struct boot_mode soc_boot_modes[] = { |
| 529 | {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, |
| 530 | /* reserved value should start rom usb */ |
Stefan Agner | 6b46c46 | 2017-06-09 13:13:12 -0700 | [diff] [blame] | 531 | #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) |
| 532 | {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, |
| 533 | #else |
Stefan Agner | eb4b62b | 2016-09-15 15:04:39 -0700 | [diff] [blame] | 534 | {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, |
Stefan Agner | 6b46c46 | 2017-06-09 13:13:12 -0700 | [diff] [blame] | 535 | #endif |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 536 | {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, |
Nikolay Dimitrov | 284d901 | 2014-08-10 20:03:07 +0300 | [diff] [blame] | 537 | {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, |
| 538 | {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, |
| 539 | {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, |
| 540 | {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 541 | /* 4 bit bus width */ |
| 542 | {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, |
| 543 | {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| 544 | {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
| 545 | {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
| 546 | {NULL, 0}, |
| 547 | }; |
Anatolij Gustschin | 938734e | 2017-08-28 17:51:33 +0200 | [diff] [blame] | 548 | #endif |
Stephen Warren | 57ab23f | 2013-02-26 12:28:29 +0000 | [diff] [blame] | 549 | |
Peng Fan | 92683e6 | 2015-10-29 15:54:50 +0800 | [diff] [blame] | 550 | void reset_misc(void) |
| 551 | { |
| 552 | #ifdef CONFIG_VIDEO_MXS |
| 553 | lcdif_power_down(); |
| 554 | #endif |
| 555 | } |
| 556 | |
Stephen Warren | 57ab23f | 2013-02-26 12:28:29 +0000 | [diff] [blame] | 557 | void s_init(void) |
| 558 | { |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 559 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 560 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 561 | u32 mask480; |
| 562 | u32 mask528; |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 563 | u32 reg, periph1, periph2; |
Fabio Estevam | 6633e3f | 2014-07-09 16:13:29 -0300 | [diff] [blame] | 564 | |
Peng Fan | 81224c4 | 2017-08-08 16:21:35 +0800 | [diff] [blame] | 565 | if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll()) |
Fabio Estevam | 6633e3f | 2014-07-09 16:13:29 -0300 | [diff] [blame] | 566 | return; |
| 567 | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 568 | /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs |
| 569 | * to make sure PFD is working right, otherwise, PFDs may |
| 570 | * not output clock after reset, MX6DL and MX6SL have added 396M pfd |
| 571 | * workaround in ROM code, as bus clock need it |
| 572 | */ |
| 573 | |
| 574 | mask480 = ANATOP_PFD_CLKGATE_MASK(0) | |
| 575 | ANATOP_PFD_CLKGATE_MASK(1) | |
| 576 | ANATOP_PFD_CLKGATE_MASK(2) | |
| 577 | ANATOP_PFD_CLKGATE_MASK(3); |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 578 | mask528 = ANATOP_PFD_CLKGATE_MASK(1) | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 579 | ANATOP_PFD_CLKGATE_MASK(3); |
| 580 | |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 581 | reg = readl(&ccm->cbcmr); |
| 582 | periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) |
| 583 | >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); |
| 584 | periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) |
| 585 | >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); |
| 586 | |
| 587 | /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ |
| 588 | if ((periph2 != 0x2) && (periph1 != 0x2)) |
| 589 | mask528 |= ANATOP_PFD_CLKGATE_MASK(0); |
| 590 | |
| 591 | if ((periph2 != 0x1) && (periph1 != 0x1) && |
| 592 | (periph2 != 0x3) && (periph1 != 0x3)) |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 593 | mask528 |= ANATOP_PFD_CLKGATE_MASK(2); |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 594 | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 595 | writel(mask480, &anatop->pfd_480_set); |
| 596 | writel(mask528, &anatop->pfd_528_set); |
| 597 | writel(mask480, &anatop->pfd_480_clr); |
| 598 | writel(mask528, &anatop->pfd_528_clr); |
Stephen Warren | 57ab23f | 2013-02-26 12:28:29 +0000 | [diff] [blame] | 599 | } |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 600 | |
| 601 | #ifdef CONFIG_IMX_HDMI |
| 602 | void imx_enable_hdmi_phy(void) |
| 603 | { |
| 604 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
| 605 | u8 reg; |
| 606 | reg = readb(&hdmi->phy_conf0); |
| 607 | reg |= HDMI_PHY_CONF0_PDZ_MASK; |
| 608 | writeb(reg, &hdmi->phy_conf0); |
| 609 | udelay(3000); |
| 610 | reg |= HDMI_PHY_CONF0_ENTMDS_MASK; |
| 611 | writeb(reg, &hdmi->phy_conf0); |
| 612 | udelay(3000); |
| 613 | reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; |
| 614 | writeb(reg, &hdmi->phy_conf0); |
| 615 | writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); |
| 616 | } |
| 617 | |
| 618 | void imx_setup_hdmi(void) |
| 619 | { |
| 620 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 621 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
Peng Fan | 95ae612 | 2016-03-09 16:07:23 +0800 | [diff] [blame] | 622 | int reg, count; |
| 623 | u8 val; |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 624 | |
| 625 | /* Turn on HDMI PHY clock */ |
| 626 | reg = readl(&mxc_ccm->CCGR2); |
| 627 | reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| |
| 628 | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; |
| 629 | writel(reg, &mxc_ccm->CCGR2); |
| 630 | writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); |
| 631 | reg = readl(&mxc_ccm->chsccdr); |
| 632 | reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| |
| 633 | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| |
| 634 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); |
| 635 | reg |= (CHSCCDR_PODF_DIVIDE_BY_3 |
| 636 | << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
| 637 | |(CHSCCDR_IPU_PRE_CLK_540M_PFD |
| 638 | << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); |
| 639 | writel(reg, &mxc_ccm->chsccdr); |
Peng Fan | 95ae612 | 2016-03-09 16:07:23 +0800 | [diff] [blame] | 640 | |
| 641 | /* Clear the overflow condition */ |
| 642 | if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { |
| 643 | /* TMDS software reset */ |
| 644 | writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); |
| 645 | val = readb(&hdmi->fc_invidconf); |
| 646 | /* Need minimum 3 times to write to clear the register */ |
| 647 | for (count = 0 ; count < 5 ; count++) |
| 648 | writeb(val, &hdmi->fc_invidconf); |
| 649 | } |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 650 | } |
| 651 | #endif |
Peng Fan | fb3a3b7 | 2016-01-28 16:55:05 +0800 | [diff] [blame] | 652 | |
Breno Lima | f22b109 | 2017-08-24 10:00:16 -0300 | [diff] [blame] | 653 | void gpr_init(void) |
| 654 | { |
| 655 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 656 | |
| 657 | /* enable AXI cache for VDOA/VPU/IPU */ |
| 658 | writel(0xF00000CF, &iomux->gpr[4]); |
| 659 | if (is_mx6dqp()) { |
| 660 | /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ |
| 661 | writel(0x77177717, &iomux->gpr[6]); |
| 662 | writel(0x77177717, &iomux->gpr[7]); |
| 663 | } else { |
| 664 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
| 665 | writel(0x007F007F, &iomux->gpr[6]); |
| 666 | writel(0x007F007F, &iomux->gpr[7]); |
| 667 | } |
| 668 | } |