Stefan Roese | 5ecdbae | 2008-06-24 17:15:22 +0200 | [diff] [blame] | 1 | #include <asm/types.h> |
wdenk | d9fce81 | 2003-06-28 17:24:46 +0000 | [diff] [blame] | 2 | #include <asm/u-boot.h> |
| 3 | #include <asm/processor.h> |
| 4 | #include <common.h> |
| 5 | #include "exbitgen.h" |
| 6 | |
Stefan Roese | cdb0470 | 2008-06-02 17:37:28 +0200 | [diff] [blame] | 7 | void sdram_init(void); |
| 8 | |
wdenk | d9fce81 | 2003-06-28 17:24:46 +0000 | [diff] [blame] | 9 | /* ************************************************************************ */ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 10 | int board_early_init_f (void) |
wdenk | d9fce81 | 2003-06-28 17:24:46 +0000 | [diff] [blame] | 11 | /* ------------------------------------------------------------------------ -- |
| 12 | * Purpose : |
| 13 | * Remarks : |
| 14 | * Restrictions: |
| 15 | * See also : |
| 16 | * Example : |
| 17 | * ************************************************************************ */ |
| 18 | { |
| 19 | unsigned long i; |
| 20 | |
| 21 | /*-------------------------------------------------------------------------+ |
| 22 | | Interrupt controller setup for the Walnut board. |
| 23 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive |
| 24 | | IRQ 16 405GP internally generated; active low; level sensitive |
| 25 | | IRQ 17-24 RESERVED |
| 26 | | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive |
| 27 | | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive |
| 28 | | IRQ 27 (EXT IRQ 2) Not Used |
| 29 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive |
| 30 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive |
| 31 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive |
| 32 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive |
| 33 | | Note for Walnut board: |
| 34 | | An interrupt taken for the FPGA (IRQ 25) indicates that either |
| 35 | | the Mouse, Keyboard, IRDA, or External Expansion caused the |
| 36 | | interrupt. The FPGA must be read to determine which device |
| 37 | | caused the interrupt. The default setting of the FPGA clears |
| 38 | | |
| 39 | +-------------------------------------------------------------------------*/ |
| 40 | |
| 41 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
| 42 | mtdcr (uicer, 0x00000000); /* disable all ints */ |
| 43 | mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ |
| 44 | mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */ |
| 45 | mtdcr (uictr, 0x10000000); /* set int trigger levels */ |
| 46 | mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ |
| 47 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
| 48 | |
| 49 | /* Perform reset of PHY connected to PPC via register in CPLD */ |
| 50 | out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */ |
| 51 | for (i = 0; i < 10000000; i++) { |
| 52 | ; |
| 53 | } |
| 54 | out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */ |
| 55 | |
| 56 | return 0; |
| 57 | } |
| 58 | |
| 59 | |
| 60 | /* ************************************************************************ */ |
| 61 | int checkboard (void) |
| 62 | /* ------------------------------------------------------------------------ -- |
| 63 | * Purpose : |
| 64 | * Remarks : |
| 65 | * Restrictions: |
| 66 | * See also : |
| 67 | * Example : |
| 68 | * ************************************************************************ */ |
| 69 | { |
| 70 | printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR)); |
| 71 | return (0); |
| 72 | } |
| 73 | |
| 74 | /* ************************************************************************ */ |
Becky Bruce | bd99ae7 | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 75 | phys_size_t initdram (int board_type) |
wdenk | d9fce81 | 2003-06-28 17:24:46 +0000 | [diff] [blame] | 76 | /* ------------------------------------------------------------------------ -- |
| 77 | * Purpose : Determines size of mounted DRAM. |
| 78 | * Remarks : Size is determined by reading SDRAM configuration registers as |
| 79 | * set up by sdram_init. |
| 80 | * Restrictions: |
| 81 | * See also : |
| 82 | * Example : |
| 83 | * ************************************************************************ */ |
| 84 | { |
| 85 | ulong tot_size; |
| 86 | ulong bank_size; |
| 87 | ulong tmp; |
| 88 | |
Stefan Roese | cdb0470 | 2008-06-02 17:37:28 +0200 | [diff] [blame] | 89 | /* |
| 90 | * ToDo: Move the asm init routine sdram_init() to this C file, |
| 91 | * or even better use some common ppc4xx code available |
| 92 | * in cpu/ppc4xx |
| 93 | */ |
| 94 | sdram_init(); |
| 95 | |
wdenk | d9fce81 | 2003-06-28 17:24:46 +0000 | [diff] [blame] | 96 | tot_size = 0; |
| 97 | |
| 98 | mtdcr (memcfga, mem_mb0cf); |
| 99 | tmp = mfdcr (memcfgd); |
| 100 | if (tmp & 0x00000001) { |
| 101 | bank_size = 0x00400000 << ((tmp >> 17) & 0x7); |
| 102 | tot_size += bank_size; |
| 103 | } |
| 104 | |
| 105 | mtdcr (memcfga, mem_mb1cf); |
| 106 | tmp = mfdcr (memcfgd); |
| 107 | if (tmp & 0x00000001) { |
| 108 | bank_size = 0x00400000 << ((tmp >> 17) & 0x7); |
| 109 | tot_size += bank_size; |
| 110 | } |
| 111 | |
| 112 | mtdcr (memcfga, mem_mb2cf); |
| 113 | tmp = mfdcr (memcfgd); |
| 114 | if (tmp & 0x00000001) { |
| 115 | bank_size = 0x00400000 << ((tmp >> 17) & 0x7); |
| 116 | tot_size += bank_size; |
| 117 | } |
| 118 | |
| 119 | mtdcr (memcfga, mem_mb3cf); |
| 120 | tmp = mfdcr (memcfgd); |
| 121 | if (tmp & 0x00000001) { |
| 122 | bank_size = 0x00400000 << ((tmp >> 17) & 0x7); |
| 123 | tot_size += bank_size; |
| 124 | } |
| 125 | |
| 126 | return tot_size; |
| 127 | } |