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git01.mediatek.com / filogic / uboot / 6dc8d7e1c6781e28b2115c4265d7809d98b5586e / . / arch / arm / dts / stm32mp15-pinctrl.dtsi
blob: c385896ebcf192424960e8bc3033f1c8ecb77a5a [file] [log] [blame]
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
9 adc1_in6_pins_a: adc1-in6 {
10 pins {
11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
12 };
13 };
14
15 adc12_ain_pins_a: adc12-ain-0 {
16 pins {
17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
21 };
22 };
23
24 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
25 pins {
26 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
27 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
28 };
29 };
30
31 cec_pins_a: cec-0 {
32 pins {
33 pinmux = <STM32_PINMUX('A', 15, AF4)>;
34 bias-disable;
35 drive-open-drain;
36 slew-rate = <0>;
37 };
38 };
39
40 cec_pins_sleep_a: cec-sleep-0 {
41 pins {
42 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
43 };
44 };
45
46 cec_pins_b: cec-1 {
47 pins {
48 pinmux = <STM32_PINMUX('B', 6, AF5)>;
49 bias-disable;
50 drive-open-drain;
51 slew-rate = <0>;
52 };
53 };
54
55 cec_pins_sleep_b: cec-sleep-1 {
56 pins {
57 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
58 };
59 };
60
61 dac_ch1_pins_a: dac-ch1 {
62 pins {
63 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
64 };
65 };
66
67 dac_ch2_pins_a: dac-ch2 {
68 pins {
69 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
70 };
71 };
72
73 dcmi_pins_a: dcmi-0 {
74 pins {
75 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
76 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
77 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
78 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
79 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
80 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
81 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
82 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
83 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
84 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
85 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
86 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
87 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
88 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
89 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
90 bias-disable;
91 };
92 };
93
94 dcmi_sleep_pins_a: dcmi-sleep-0 {
95 pins {
96 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
97 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
98 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
99 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
100 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
101 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
102 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
103 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
104 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
105 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
106 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
107 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
108 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
109 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
110 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
111 };
112 };
113
114 ethernet0_rgmii_pins_a: rgmii-0 {
115 pins1 {
116 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
117 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
118 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
119 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
120 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
121 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
122 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
123 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
124 bias-disable;
125 drive-push-pull;
126 slew-rate = <2>;
127 };
128 pins2 {
129 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
130 bias-disable;
131 drive-push-pull;
132 slew-rate = <0>;
133 };
134 pins3 {
135 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
136 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
137 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
138 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
139 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
140 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
141 bias-disable;
142 };
143 };
144
145 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
146 pins1 {
147 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
148 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
149 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
150 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
151 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
152 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
153 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
154 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
155 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
156 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
157 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
158 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
159 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
160 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
161 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
162 };
163 };
164
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]165 ethernet0_rgmii_pins_b: rgmii-1 {
166 pins1 {
167 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
168 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
169 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
170 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
171 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
172 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
173 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
174 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
175 bias-disable;
176 drive-push-pull;
177 slew-rate = <2>;
178 };
179 pins2 {
180 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
181 bias-disable;
182 drive-push-pull;
183 slew-rate = <0>;
184 };
185 pins3 {
186 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
187 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
188 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
189 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
190 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
191 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
192 bias-disable;
193 };
194 };
195
196 ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 {
197 pins1 {
198 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
199 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
200 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
201 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
202 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
203 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
204 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
205 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
206 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
207 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
208 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
209 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
210 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
211 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
212 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
213 };
214 };
215
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]216 ethernet0_rmii_pins_a: rmii-0 {
217 pins1 {
218 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
219 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
220 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
221 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
222 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
223 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
224 bias-disable;
225 drive-push-pull;
226 slew-rate = <2>;
227 };
228 pins2 {
229 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
230 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
231 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
232 bias-disable;
233 };
234 };
235
236 ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
237 pins1 {
238 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
239 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
240 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
241 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
242 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
243 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
244 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
245 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
246 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
247 };
248 };
249
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]250 fmc_pins_a: fmc-0 {
251 pins1 {
252 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
253 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
254 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
255 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
256 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
257 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
258 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
259 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
260 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
261 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
262 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
263 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
264 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
265 bias-disable;
266 drive-push-pull;
267 slew-rate = <1>;
268 };
269 pins2 {
270 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
271 bias-pull-up;
272 };
273 };
274
275 fmc_sleep_pins_a: fmc-sleep-0 {
276 pins {
277 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
278 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
279 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
280 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
281 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
282 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
283 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
284 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
285 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
286 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
287 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
288 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
289 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
290 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
291 };
292 };
293
294 i2c1_pins_a: i2c1-0 {
295 pins {
296 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
297 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
298 bias-disable;
299 drive-open-drain;
300 slew-rate = <0>;
301 };
302 };
303
304 i2c1_pins_sleep_a: i2c1-1 {
305 pins {
306 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
307 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
308 };
309 };
310
311 i2c1_pins_b: i2c1-2 {
312 pins {
313 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
314 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
315 bias-disable;
316 drive-open-drain;
317 slew-rate = <0>;
318 };
319 };
320
321 i2c1_pins_sleep_b: i2c1-3 {
322 pins {
323 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
324 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
325 };
326 };
327
328 i2c2_pins_a: i2c2-0 {
329 pins {
330 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
331 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
332 bias-disable;
333 drive-open-drain;
334 slew-rate = <0>;
335 };
336 };
337
338 i2c2_pins_sleep_a: i2c2-1 {
339 pins {
340 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
341 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
342 };
343 };
344
345 i2c2_pins_b1: i2c2-2 {
346 pins {
347 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
348 bias-disable;
349 drive-open-drain;
350 slew-rate = <0>;
351 };
352 };
353
354 i2c2_pins_sleep_b1: i2c2-3 {
355 pins {
356 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
357 };
358 };
359
Marek Vasutda779092020-05-26 04:30:21 +0200[diff] [blame]360 i2c2_pins_c: i2c2-4 {
361 pins {
362 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
363 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
364 bias-disable;
365 drive-open-drain;
366 slew-rate = <0>;
367 };
368 };
369
370 i2c2_pins_sleep_c: i2c2-5 {
371 pins {
372 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
373 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
374 };
375 };
376
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]377 i2c5_pins_a: i2c5-0 {
378 pins {
379 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
380 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
381 bias-disable;
382 drive-open-drain;
383 slew-rate = <0>;
384 };
385 };
386
387 i2c5_pins_sleep_a: i2c5-1 {
388 pins {
389 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
390 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
391
392 };
393 };
394
395 i2s2_pins_a: i2s2-0 {
396 pins {
397 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
398 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
399 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
400 slew-rate = <1>;
401 drive-push-pull;
402 bias-disable;
403 };
404 };
405
406 i2s2_pins_sleep_a: i2s2-1 {
407 pins {
408 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
409 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
410 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
411 };
412 };
413
414 ltdc_pins_a: ltdc-a-0 {
415 pins {
416 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
417 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
418 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
419 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
420 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
421 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
422 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
423 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
424 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
425 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
426 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
427 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
428 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
429 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
430 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
431 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
432 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
433 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
434 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
435 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
436 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
437 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
438 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
439 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
440 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
441 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
442 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
443 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
444 bias-disable;
445 drive-push-pull;
446 slew-rate = <1>;
447 };
448 };
449
450 ltdc_pins_sleep_a: ltdc-a-1 {
451 pins {
452 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
453 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
454 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
455 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
456 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
457 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
458 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
459 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
460 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
461 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
462 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
463 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
464 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
465 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
466 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
467 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
468 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
469 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
470 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
471 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
472 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
473 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
474 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
475 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
476 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
477 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
478 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
479 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
480 };
481 };
482
483 ltdc_pins_b: ltdc-b-0 {
484 pins {
485 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
486 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
487 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
488 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
489 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
490 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
491 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
492 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
493 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
494 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
495 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
496 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
497 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
498 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
499 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
500 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
501 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
502 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
503 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
504 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
505 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
506 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
507 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
508 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
509 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
510 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
511 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
512 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
513 bias-disable;
514 drive-push-pull;
515 slew-rate = <1>;
516 };
517 };
518
519 ltdc_pins_sleep_b: ltdc-b-1 {
520 pins {
521 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
522 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
523 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
524 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
525 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
526 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
527 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
528 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
529 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
530 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
531 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
532 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
533 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
534 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
535 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
536 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
537 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
538 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
539 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
540 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
541 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
542 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
543 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
544 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
545 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
546 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
547 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
548 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
549 };
550 };
551
552 m_can1_pins_a: m-can1-0 {
553 pins1 {
554 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
555 slew-rate = <1>;
556 drive-push-pull;
557 bias-disable;
558 };
559 pins2 {
560 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
561 bias-disable;
562 };
563 };
564
565 m_can1_sleep_pins_a: m_can1-sleep-0 {
566 pins {
567 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
568 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
569 };
570 };
571
572 pwm1_pins_a: pwm1-0 {
573 pins {
574 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
575 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
576 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
577 bias-pull-down;
578 drive-push-pull;
579 slew-rate = <0>;
580 };
581 };
582
583 pwm1_sleep_pins_a: pwm1-sleep-0 {
584 pins {
585 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
586 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
587 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
588 };
589 };
590
591 pwm2_pins_a: pwm2-0 {
592 pins {
593 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
594 bias-pull-down;
595 drive-push-pull;
596 slew-rate = <0>;
597 };
598 };
599
600 pwm2_sleep_pins_a: pwm2-sleep-0 {
601 pins {
602 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
603 };
604 };
605
606 pwm3_pins_a: pwm3-0 {
607 pins {
608 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
609 bias-pull-down;
610 drive-push-pull;
611 slew-rate = <0>;
612 };
613 };
614
615 pwm3_sleep_pins_a: pwm3-sleep-0 {
616 pins {
617 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
618 };
619 };
620
621 pwm4_pins_a: pwm4-0 {
622 pins {
623 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
624 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
625 bias-pull-down;
626 drive-push-pull;
627 slew-rate = <0>;
628 };
629 };
630
631 pwm4_sleep_pins_a: pwm4-sleep-0 {
632 pins {
633 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
634 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
635 };
636 };
637
638 pwm4_pins_b: pwm4-1 {
639 pins {
640 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
641 bias-pull-down;
642 drive-push-pull;
643 slew-rate = <0>;
644 };
645 };
646
647 pwm4_sleep_pins_b: pwm4-sleep-1 {
648 pins {
649 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
650 };
651 };
652
653 pwm5_pins_a: pwm5-0 {
654 pins {
655 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
656 bias-pull-down;
657 drive-push-pull;
658 slew-rate = <0>;
659 };
660 };
661
662 pwm5_sleep_pins_a: pwm5-sleep-0 {
663 pins {
664 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
665 };
666 };
667
668 pwm8_pins_a: pwm8-0 {
669 pins {
670 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
671 bias-pull-down;
672 drive-push-pull;
673 slew-rate = <0>;
674 };
675 };
676
677 pwm8_sleep_pins_a: pwm8-sleep-0 {
678 pins {
679 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
680 };
681 };
682
683 pwm12_pins_a: pwm12-0 {
684 pins {
685 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
686 bias-pull-down;
687 drive-push-pull;
688 slew-rate = <0>;
689 };
690 };
691
692 pwm12_sleep_pins_a: pwm12-sleep-0 {
693 pins {
694 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
695 };
696 };
697
698 qspi_clk_pins_a: qspi-clk-0 {
699 pins {
700 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
701 bias-disable;
702 drive-push-pull;
703 slew-rate = <3>;
704 };
705 };
706
707 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
708 pins {
709 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
710 };
711 };
712
713 qspi_bk1_pins_a: qspi-bk1-0 {
714 pins1 {
715 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
716 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
717 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
718 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
719 bias-disable;
720 drive-push-pull;
721 slew-rate = <1>;
722 };
723 pins2 {
724 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
725 bias-pull-up;
726 drive-push-pull;
727 slew-rate = <1>;
728 };
729 };
730
731 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
732 pins {
733 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
734 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
735 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
736 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
737 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
738 };
739 };
740
741 qspi_bk2_pins_a: qspi-bk2-0 {
742 pins1 {
743 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
744 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
745 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
746 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
747 bias-disable;
748 drive-push-pull;
749 slew-rate = <1>;
750 };
751 pins2 {
752 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
753 bias-pull-up;
754 drive-push-pull;
755 slew-rate = <1>;
756 };
757 };
758
759 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
760 pins {
761 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
762 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
763 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
764 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
765 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
766 };
767 };
768
769 sai2a_pins_a: sai2a-0 {
770 pins {
771 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
772 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
773 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
774 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
775 slew-rate = <0>;
776 drive-push-pull;
777 bias-disable;
778 };
779 };
780
781 sai2a_sleep_pins_a: sai2a-1 {
782 pins {
783 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
784 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
785 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
786 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
787 };
788 };
789
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]790 sai2a_pins_b: sai2a-2 {
791 pins1 {
792 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
793 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
794 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
795 slew-rate = <0>;
796 drive-push-pull;
797 bias-disable;
798 };
799 };
800
801 sai2a_sleep_pins_b: sai2a-sleep-3 {
802 pins {
803 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
804 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
805 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
806 };
807 };
808
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]809 sai2b_pins_a: sai2b-0 {
810 pins1 {
811 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
812 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
813 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
814 slew-rate = <0>;
815 drive-push-pull;
816 bias-disable;
817 };
818 pins2 {
819 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
820 bias-disable;
821 };
822 };
823
824 sai2b_sleep_pins_a: sai2b-1 {
825 pins {
826 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
827 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
828 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
829 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
830 };
831 };
832
833 sai2b_pins_b: sai2b-2 {
834 pins {
835 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
836 bias-disable;
837 };
838 };
839
840 sai2b_sleep_pins_b: sai2b-3 {
841 pins {
842 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
843 };
844 };
845
846 sai4a_pins_a: sai4a-0 {
847 pins {
848 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
849 slew-rate = <0>;
850 drive-push-pull;
851 bias-disable;
852 };
853 };
854
855 sai4a_sleep_pins_a: sai4a-1 {
856 pins {
857 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
858 };
859 };
860
861 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
862 pins1 {
863 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
864 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
865 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
866 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
867 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
868 slew-rate = <1>;
869 drive-push-pull;
870 bias-disable;
871 };
872 pins2 {
873 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
874 slew-rate = <2>;
875 drive-push-pull;
876 bias-disable;
877 };
878 };
879
880 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
881 pins1 {
882 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
883 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
884 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
885 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
886 slew-rate = <1>;
887 drive-push-pull;
888 bias-disable;
889 };
890 pins2 {
891 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
892 slew-rate = <2>;
893 drive-push-pull;
894 bias-disable;
895 };
896 pins3 {
897 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
898 slew-rate = <1>;
899 drive-open-drain;
900 bias-disable;
901 };
902 };
903
904 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
905 pins {
906 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
907 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
908 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
909 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
910 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
911 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
912 };
913 };
914
915 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
916 pins1 {
917 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
918 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
919 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
920 slew-rate = <1>;
921 drive-push-pull;
922 bias-pull-up;
923 };
924 pins2{
925 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
926 bias-pull-up;
927 };
928 };
929
930 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
931 pins {
932 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
933 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
934 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
935 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
936 };
937 };
938
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]939 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
940 pins1 {
941 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
942 <STM32_PINMUX('E', 14, AF8)>, /* SDMMC1_D123DIR */
943 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
944 slew-rate = <1>;
945 drive-push-pull;
946 bias-pull-up;
947 };
948 pins2{
949 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
950 bias-pull-up;
951 };
952 };
953
954 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
955 pins {
956 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
957 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
958 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
959 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
960 };
961 };
962
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]963 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
964 pins1 {
965 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
966 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
967 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
968 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
969 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
970 slew-rate = <1>;
971 drive-push-pull;
972 bias-pull-up;
973 };
974 pins2 {
975 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
976 slew-rate = <2>;
977 drive-push-pull;
978 bias-pull-up;
979 };
980 };
981
982 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
983 pins1 {
984 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
985 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
986 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
987 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
988 slew-rate = <1>;
989 drive-push-pull;
990 bias-pull-up;
991 };
992 pins2 {
993 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
994 slew-rate = <2>;
995 drive-push-pull;
996 bias-pull-up;
997 };
998 pins3 {
999 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1000 slew-rate = <1>;
1001 drive-open-drain;
1002 bias-pull-up;
1003 };
1004 };
1005
1006 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
1007 pins {
1008 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
1009 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
1010 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
1011 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
1012 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
1013 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
1014 };
1015 };
1016
1017 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
1018 pins1 {
1019 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1020 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1021 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1022 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
1023 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1024 slew-rate = <1>;
1025 drive-push-pull;
1026 bias-disable;
1027 };
1028 pins2 {
1029 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1030 slew-rate = <2>;
1031 drive-push-pull;
1032 bias-disable;
1033 };
1034 };
1035
1036 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
1037 pins1 {
1038 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1039 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1040 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1041 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
1042 slew-rate = <1>;
1043 drive-push-pull;
1044 bias-disable;
1045 };
1046 pins2 {
1047 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1048 slew-rate = <2>;
1049 drive-push-pull;
1050 bias-disable;
1051 };
1052 pins3 {
1053 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1054 slew-rate = <1>;
1055 drive-open-drain;
1056 bias-disable;
1057 };
1058 };
1059
1060 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
1061 pins {
1062 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1063 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1064 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
1065 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
1066 slew-rate = <1>;
1067 drive-push-pull;
1068 bias-pull-up;
1069 };
1070 };
1071
1072 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
1073 pins {
1074 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1075 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1076 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
1077 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
1078 };
1079 };
1080
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1081 sdmmc2_d47_pins_b: sdmmc2-d47-1 {
1082 pins {
1083 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1084 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
1085 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
1086 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
1087 slew-rate = <1>;
1088 drive-push-pull;
1089 bias-pull-up;
1090 };
1091 };
1092
1093 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
1094 pins {
1095 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1096 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
1097 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
1098 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
1099 };
1100 };
1101
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1102 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
1103 pins1 {
1104 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1105 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1106 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1107 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
1108 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
1109 slew-rate = <1>;
1110 drive-push-pull;
1111 bias-pull-up;
1112 };
1113 pins2 {
1114 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1115 slew-rate = <2>;
1116 drive-push-pull;
1117 bias-pull-up;
1118 };
1119 };
1120
1121 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
1122 pins1 {
1123 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1124 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1125 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1126 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
1127 slew-rate = <1>;
1128 drive-push-pull;
1129 bias-pull-up;
1130 };
1131 pins2 {
1132 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1133 slew-rate = <2>;
1134 drive-push-pull;
1135 bias-pull-up;
1136 };
1137 pins3 {
1138 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
1139 slew-rate = <1>;
1140 drive-open-drain;
1141 bias-pull-up;
1142 };
1143 };
1144
1145 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
1146 pins {
1147 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1148 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1149 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
1150 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
1151 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
1152 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
1153 };
1154 };
1155
1156 spdifrx_pins_a: spdifrx-0 {
1157 pins {
1158 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
1159 bias-disable;
1160 };
1161 };
1162
1163 spdifrx_sleep_pins_a: spdifrx-1 {
1164 pins {
1165 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
1166 };
1167 };
1168
1169 spi2_pins_a: spi2-0 {
1170 pins1 {
1171 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
1172 <STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */
1173 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
1174 bias-disable;
1175 drive-push-pull;
1176 slew-rate = <3>;
1177 };
1178 pins2 {
1179 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
1180 bias-disable;
1181 };
1182 };
1183
1184 stusb1600_pins_a: stusb1600-0 {
1185 pins {
1186 pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
1187 bias-pull-up;
1188 };
1189 };
1190
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]1191 usart3_pins_a: usart3-0 {
1192 pins1 {
1193 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
1194 bias-disable;
1195 drive-push-pull;
1196 slew-rate = <0>;
1197 };
1198 pins2 {
1199 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
1200 bias-disable;
1201 };
1202 };
1203
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1204 uart4_pins_a: uart4-0 {
1205 pins1 {
1206 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
1207 bias-disable;
1208 drive-push-pull;
1209 slew-rate = <0>;
1210 };
1211 pins2 {
1212 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1213 bias-disable;
1214 };
1215 };
1216
1217 uart4_pins_b: uart4-1 {
1218 pins1 {
1219 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
1220 bias-disable;
1221 drive-push-pull;
1222 slew-rate = <0>;
1223 };
1224 pins2 {
1225 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1226 bias-disable;
1227 };
1228 };
1229
1230 uart7_pins_a: uart7-0 {
1231 pins1 {
1232 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
1233 bias-disable;
1234 drive-push-pull;
1235 slew-rate = <0>;
1236 };
1237 pins2 {
1238 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
1239 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
1240 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
1241 bias-disable;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]1242 };
1243 };
1244
1245 uart8_pins_a: uart8-0 {
1246 pins1 {
1247 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
1248 bias-disable;
1249 drive-push-pull;
1250 slew-rate = <0>;
1251 };
1252 pins2 {
1253 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
1254 bias-disable;
1255 };
1256 };
1257
1258 usbotg_hs_pins_a: usbotg-hs-0 {
1259 pins {
1260 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
1261 };
1262 };
1263
1264 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
1265 pins {
1266 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
1267 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1268 };
1269 };
1270};
1271
1272&pinctrl_z {
1273 i2c2_pins_b2: i2c2-0 {
1274 pins {
1275 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
1276 bias-disable;
1277 drive-open-drain;
1278 slew-rate = <0>;
1279 };
1280 };
1281
1282 i2c2_pins_sleep_b2: i2c2-1 {
1283 pins {
1284 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
1285 };
1286 };
1287
1288 i2c4_pins_a: i2c4-0 {
1289 pins {
1290 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
1291 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
1292 bias-disable;
1293 drive-open-drain;
1294 slew-rate = <0>;
1295 };
1296 };
1297
1298 i2c4_pins_sleep_a: i2c4-1 {
1299 pins {
1300 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
1301 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
1302 };
1303 };
1304
1305 spi1_pins_a: spi1-0 {
1306 pins1 {
1307 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
1308 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
1309 bias-disable;
1310 drive-push-pull;
1311 slew-rate = <1>;
1312 };
1313
1314 pins2 {
1315 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
1316 bias-disable;
1317 };
1318 };
1319};