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git01.mediatek.com / filogic / uboot / 6dc8d7e1c6781e28b2115c4265d7809d98b5586e / . / arch / arm / dts / imx6sx-softing-vining-2000.dts
blob: 78dd5755a379b216ed6eab87779b22e39a65664c [file] [log] [blame]
Marek Vasut29163bd2019-05-17 22:25:22 +0200[diff] [blame]1/*
2 * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "imx6sx.dtsi"
14
15/ {
16 model = "Softing VIN|ING 2000";
17 compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
18
Marek Vasutf953c992019-05-17 22:25:24 +0200[diff] [blame]19 aliases {
20 mmc0 = &usdhc4;
21 mmc1 = &usdhc2;
22 };
23
Marek Vasut29163bd2019-05-17 22:25:22 +0200[diff] [blame]24 chosen {
25 stdout-path = &uart1;
26 };
27
28 memory@80000000 {
29 device_type = "memory";
30 reg = <0x80000000 0x40000000>;
31 };
32
33 reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
34 compatible = "regulator-fixed";
35 regulator-name = "usb_otg1_vbus";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_usb_otg1>;
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
41 enable-active-high;
42 };
43
44 reg_peri_3v3: regulator-peri_3v3 {
45 compatible = "regulator-fixed";
46 regulator-name = "peri_3v3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 };
50
51 pwmleds {
52 compatible = "pwm-leds";
53
54 red {
55 label = "red";
56 max-brightness = <255>;
57 pwms = <&pwm6 0 50000>;
58 };
59
60 green {
61 label = "green";
62 max-brightness = <255>;
63 pwms = <&pwm2 0 50000>;
64 };
65
66 blue {
67 label = "blue";
68 max-brightness = <255>;
69 pwms = <&pwm1 0 50000>;
70 };
71 };
72};
73
74&adc1 {
75 vref-supply = <&reg_peri_3v3>;
76 status = "okay";
77};
78
79&cpu0 {
80 /*
81 * This board has a shared rail of reg_arm and reg_soc (supplied by
82 * sw1a_reg) which is modeled below, but still this module behaves
83 * unstable without higher voltages. Hence, set higher voltages here.
84 */
85 operating-points = <
86 /* kHz uV */
87 996000 1250000
88 792000 1175000
89 396000 1175000
90 198000 1175000
91 >;
92 fsl,soc-operating-points = <
93 /* ARM kHz SOC uV */
94 996000 1250000
95 792000 1175000
96 396000 1175000
97 198000 1175000
98 >;
99};
100
101&ecspi4 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ecspi4>;
104 cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
105 status = "okay";
106};
107
108&fec1 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_enet1>;
111 phy-supply = <&reg_peri_3v3>;
112 phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
113 phy-reset-duration = <5>;
114 phy-mode = "rmii";
115 phy-handle = <&ethphy0>;
116 status = "okay";
117
118 mdio {
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 ethphy0: ethernet0-phy@0 {
123 reg = <0>;
124 max-speed = <100>;
125 interrupt-parent = <&gpio2>;
126 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
127 };
128 };
129};
130
131&fec2 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_enet2>;
134 phy-supply = <&reg_peri_3v3>;
135 phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
136 phy-reset-duration = <5>;
137 phy-mode = "rmii";
138 phy-handle = <&ethphy1>;
139 status = "okay";
140
141 mdio {
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 ethphy1: ethernet1-phy@0 {
146 reg = <0>;
147 max-speed = <100>;
148 interrupt-parent = <&gpio2>;
149 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
150 };
151 };
152};
153
154&flexcan1 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_flexcan1>;
157 status = "okay";
158};
159
160&flexcan2 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_flexcan2>;
163 status = "okay";
164};
165
166&i2c1 {
167 clock-frequency = <100000>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
170 status = "okay";
171
172 proximity: sx9500@28 {
173 compatible = "semtech,sx9500";
174 reg = <0x28>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_sx9500>;
177 interrupt-parent = <&gpio2>;
178 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
179 reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
180 };
181
182 pmic: pfuze100@8 {
183 compatible = "fsl,pfuze200";
184 reg = <0x08>;
185
186 regulators {
187 sw1a_reg: sw1ab {
188 regulator-min-microvolt = <300000>;
189 regulator-max-microvolt = <1875000>;
190 regulator-boot-on;
191 regulator-always-on;
192 regulator-ramp-delay = <6250>;
193 };
194
195 sw2_reg: sw2 {
196 regulator-min-microvolt = <800000>;
197 regulator-max-microvolt = <3300000>;
198 regulator-boot-on;
199 regulator-always-on;
200 };
201
202 sw3a_reg: sw3a {
203 regulator-min-microvolt = <400000>;
204 regulator-max-microvolt = <1975000>;
205 regulator-boot-on;
206 regulator-always-on;
207 };
208
209 sw3b_reg: sw3b {
210 regulator-min-microvolt = <400000>;
211 regulator-max-microvolt = <1975000>;
212 regulator-boot-on;
213 regulator-always-on;
214 };
215
216 snvs_reg: vsnvs {
217 regulator-min-microvolt = <1000000>;
218 regulator-max-microvolt = <3000000>;
219 regulator-boot-on;
220 regulator-always-on;
221 };
222
223 vref_reg: vrefddr {
224 regulator-boot-on;
225 regulator-always-on;
226 };
227
228 vgen1_reg: vgen1 {
229 regulator-min-microvolt = <800000>;
230 regulator-max-microvolt = <1550000>;
231 regulator-always-on;
232 };
233
234 vgen2_reg: vgen2 {
235 regulator-min-microvolt = <800000>;
236 regulator-max-microvolt = <1550000>;
237 };
238
239 vgen3_reg: vgen3 {
240 regulator-min-microvolt = <1800000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-always-on;
243 };
244
245 vgen4_reg: vgen4 {
246 regulator-min-microvolt = <1800000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-always-on;
249 };
250
251 vgen5_reg: vgen5 {
252 regulator-min-microvolt = <1800000>;
253 regulator-max-microvolt = <3300000>;
254 regulator-always-on;
255 };
256
257 vgen6_reg: vgen6 {
258 regulator-min-microvolt = <1800000>;
259 regulator-max-microvolt = <3300000>;
260 regulator-always-on;
261 };
262 };
263 };
264};
265
266&i2c3 {
267 clock-frequency = <100000>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c3>;
270 status = "okay";
271};
272
Marek Vasutb0f19272019-11-26 09:39:12 +0100[diff] [blame]273&reg_pcie {
274 regulator-always-on;
275};
276
277&pcie {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_pcie>;
280 reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
281 status = "okay";
282};
283
Marek Vasut29163bd2019-05-17 22:25:22 +0200[diff] [blame]284&iomuxc {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_gpios>;
287
288 pinctrl_ecspi4: ecspi4grp {
289 fsl,pins = <
290 MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1
291 MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1
292 MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1
293 MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0
294 >;
295 };
296
297 pinctrl_enet1: enet1grp {
298 fsl,pins = <
299 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1
300 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1
301 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9
302 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9
303 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1
304 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9
305 MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038
306 /* LAN8720 PHY Reset */
307 MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0
308 /* MDIO */
309 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9
310 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9
311 /* IRQ from PHY */
312 MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0
313 >;
314 };
315
316 pinctrl_enet2: enet2grp {
317 fsl,pins = <
318 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0
319 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0
320 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0
321 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0
322 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0
323 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0
324 MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038
325 /* LAN8720 PHY Reset */
326 MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0
327 /* MDIO */
328 MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9
329 MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9
330 /* IRQ from PHY */
331 MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0
332 >;
333 };
334
335 pinctrl_flexcan1: flexcan1grp {
336 fsl,pins = <
337 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
338 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
339 >;
340 };
341
342 pinctrl_flexcan2: flexcan2grp {
343 fsl,pins = <
344 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
345 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
346 >;
347 };
348
349 pinctrl_gpios: gpiosgrp {
350 fsl,pins = <
351 /* reset external uC */
352 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0
353 /* IRQ from external uC */
354 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0
355 /* overcurrent detection */
356 MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0
357 >;
358 };
359
360 pinctrl_i2c1: i2c1grp {
361 fsl,pins = <
362 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
363 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
364 >;
365 };
366
367 pinctrl_i2c3: i2c3grp {
368 fsl,pins = <
369 MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1
370 MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1
371 >;
372 };
373
Marek Vasutb0f19272019-11-26 09:39:12 +0100[diff] [blame]374 pinctrl_pcie: pciegrp {
375 fsl,pins = <
376 MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0
377 >;
378 };
379
Marek Vasut29163bd2019-05-17 22:25:22 +0200[diff] [blame]380 pinctrl_pwm1: pwm1grp-1 {
381 fsl,pins = <
382 /* blue LED */
383 MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1
384 >;
385 };
386
387 pinctrl_pwm2: pwm2grp-1 {
388 fsl,pins = <
389 /* green LED */
390 MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1
391 >;
392 };
393
394 pinctrl_pwm6: pwm6grp-1 {
395 fsl,pins = <
396 /* red LED */
397 MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1
398 >;
399 };
400
401 pinctrl_sx9500: sx9500grp {
402 fsl,pins = <
403 /* Reset */
404 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838
405 /* IRQ */
406 MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0
407 >;
408 };
409
410 pinctrl_uart1: uart1grp {
411 fsl,pins = <
412 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
413 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
414 >;
415 };
416
417 pinctrl_uart2: uart2grp {
418 fsl,pins = <
419 MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
420 MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
421 >;
422 };
423
424 pinctrl_usb_otg1: usbotg1grp {
425 fsl,pins = <
426 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
427 >;
428 };
429
430 pinctrl_usb_otg1_id: usbotg1idgrp {
431 fsl,pins = <
432 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
433 >;
434 };
435
436 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
437 fsl,pins = <
438 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
439 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
440 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
441 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
442 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
443 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
444 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000
445 MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0
446 >;
447 };
448
449 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
450 fsl,pins = <
451 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9
452 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9
453 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9
454 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9
455 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9
456 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9
457 >;
458 };
459
460 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
461 fsl,pins = <
462 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9
463 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9
464 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9
465 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9
466 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9
467 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9
468 >;
469 };
470
471 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
472 fsl,pins = <
473 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
474 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
475 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
476 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
477 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
478 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
479 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
480 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
481 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
482 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
483 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068
484 >;
485 };
486
487 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
488 fsl,pins = <
489 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
490 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
491 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
492 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
493 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
494 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
495 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
496 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
497 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
498 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
499 >;
500 };
501
502 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
503 fsl,pins = <
504 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
505 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
506 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
507 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
508 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
509 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
510 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
511 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
512 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
513 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
514 >;
515 };
516};
517
518&pwm1 {
519 pinctrl-names = "default";
520 pinctrl-0 = <&pinctrl_pwm1>;
521 status = "okay";
522};
523
524&pwm2 {
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_pwm2>;
527 status = "okay";
528};
529
530&pwm6 {
531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_pwm6>;
533 status = "okay";
534};
535
536&reg_arm {
537 vin-supply = <&sw1a_reg>;
538};
539
540&reg_soc {
541 vin-supply = <&sw1a_reg>;
542};
543
544&snvs_poweroff {
545 status = "okay";
546};
547
548&uart1 {
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_uart1>;
551 status = "okay";
552};
553
554&uart2 {
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_uart2>;
557 status = "okay";
558};
559
560&usbotg1 {
561 vbus-supply = <&reg_usb_otg1_vbus>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_usb_otg1_id>;
564 status = "okay";
565};
566
567&usbotg2 {
568 dr_mode = "host";
569 status = "okay";
570};
571
572&usdhc2 {
573 pinctrl-names = "default", "state_100mhz", "state_200mhz";
574 pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
575 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
576 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
577 cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
578 keep-power-in-suspend;
579 status = "okay";
580};
581
582&usdhc4 {
583 /* hs200-mode is currently unsupported because Vccq is on 3.1V, but
584 * not on necessary 1.8V.
585 */
586 pinctrl-names = "default", "state_100mhz", "state_200mhz";
587 pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
588 pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
589 pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
590 bus-width = <8>;
591 keep-power-in-suspend;
592 non-removable;
593 cap-mmc-hw-reset;
594 status = "okay";
595};