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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChung Liewb354aef2009-06-12 11:29:00 +00002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang95bed1f2012-03-26 21:49:04 +00006 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
TsiChung Liewb354aef2009-06-12 11:29:00 +00007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewb354aef2009-06-12 11:29:00 +00008 */
9
10#include <config.h>
11#include <common.h>
Simon Glass0ffd9db2019-12-28 10:45:06 -070012#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
TsiChung Liewb354aef2009-06-12 11:29:00 +000014#include <asm/immap.h>
Alison Wang95bed1f2012-03-26 21:49:04 +000015#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
TsiChung Liewb354aef2009-06-12 11:29:00 +000017
18DECLARE_GLOBAL_DATA_PTR;
19
20int checkboard(void)
21{
22 puts("Board: ");
23 puts("Freescale M5208EVBe\n");
24 return 0;
25};
26
Simon Glassd35f3382017-04-06 12:47:05 -060027int dram_init(void)
TsiChung Liewb354aef2009-06-12 11:29:00 +000028{
Alison Wang95bed1f2012-03-26 21:49:04 +000029 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
TsiChung Liewb354aef2009-06-12 11:29:00 +000030 u32 dramsize, i;
31
Tom Rinibb4dd962022-11-16 13:10:37 -050032 dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
TsiChung Liewb354aef2009-06-12 11:29:00 +000033
34 for (i = 0x13; i < 0x20; i++) {
35 if (dramsize == (1 << i))
36 break;
37 }
38 i--;
39
Tom Rinibb4dd962022-11-16 13:10:37 -050040 out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
41#ifdef CFG_SYS_SDRAM_BASE1
42 out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
TsiChung Liewb354aef2009-06-12 11:29:00 +000043#endif
Tom Rinibb4dd962022-11-16 13:10:37 -050044 out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
45 out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
TsiChung Liewb354aef2009-06-12 11:29:00 +000046
47 udelay(500);
48
49 /* Issue PALL */
Tom Rinibb4dd962022-11-16 13:10:37 -050050 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
TsiChung Liewb354aef2009-06-12 11:29:00 +000051 asm("nop");
52
53 /* Perform two refresh cycles */
Tom Rinibb4dd962022-11-16 13:10:37 -050054 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
55 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
TsiChung Liewb354aef2009-06-12 11:29:00 +000056 asm("nop");
57
58 /* Issue LEMR */
Tom Rinibb4dd962022-11-16 13:10:37 -050059 out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
TsiChung Liewb354aef2009-06-12 11:29:00 +000060 asm("nop");
Tom Rinibb4dd962022-11-16 13:10:37 -050061 out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
TsiChung Liewb354aef2009-06-12 11:29:00 +000062 asm("nop");
63
Tom Rinibb4dd962022-11-16 13:10:37 -050064 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
TsiChung Liewb354aef2009-06-12 11:29:00 +000065 asm("nop");
66
Alison Wang95bed1f2012-03-26 21:49:04 +000067 out_be32(&sdram->ctrl,
Tom Rinibb4dd962022-11-16 13:10:37 -050068 (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
TsiChung Liewb354aef2009-06-12 11:29:00 +000069 asm("nop");
70
71 udelay(100);
72
Simon Glass39f90ba2017-03-31 08:40:25 -060073 gd->ram_size = dramsize;
74
75 return 0;
TsiChung Liewb354aef2009-06-12 11:29:00 +000076};
77
78int testdram(void)
79{
80 /* TODO: XXX XXX XXX */
81 printf("DRAM test not implemented!\n");
82
83 return (0);
84}