Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * Dave Liu <daveliu@freescale.com> |
| 5 | * based on the contribution of Marian Balakowicz <m8@semihalf.com> |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #include <common.h> |
| 17 | #include <mpc83xx.h> |
| 18 | #include <command.h> |
| 19 | |
| 20 | #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) |
| 21 | void ecc_print_status(void) |
| 22 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 24 | volatile ddr83xx_t *ddr = &immap->ddr; |
| 25 | |
| 26 | printf("\nECC mode: %s\n\n", |
| 27 | (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); |
| 28 | |
| 29 | /* Interrupts */ |
| 30 | printf("Memory Error Interrupt Enable:\n"); |
| 31 | printf(" Multiple-Bit Error Interrupt Enable: %d\n", |
| 32 | (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); |
| 33 | printf(" Single-Bit Error Interrupt Enable: %d\n", |
| 34 | (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); |
| 35 | printf(" Memory Select Error Interrupt Enable: %d\n\n", |
| 36 | (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); |
| 37 | |
| 38 | /* Error disable */ |
| 39 | printf("Memory Error Disable:\n"); |
| 40 | printf(" Multiple-Bit Error Disable: %d\n", |
| 41 | (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); |
| 42 | printf(" Sinle-Bit Error Disable: %d\n", |
| 43 | (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); |
| 44 | printf(" Memory Select Error Disable: %d\n\n", |
| 45 | (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); |
| 46 | |
| 47 | /* Error injection */ |
Kim Phillips | f91aa8d | 2008-07-10 14:00:15 -0500 | [diff] [blame] | 48 | printf("Memory Data Path Error Injection Mask High/Low: %08x %08x\n", |
Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 49 | ddr->data_err_inject_hi, ddr->data_err_inject_lo); |
| 50 | |
| 51 | printf("Memory Data Path Error Injection Mask ECC:\n"); |
| 52 | printf(" ECC Mirror Byte: %d\n", |
| 53 | (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); |
| 54 | printf(" ECC Injection Enable: %d\n", |
| 55 | (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); |
| 56 | printf(" ECC Error Injection Mask: 0x%02x\n\n", |
| 57 | ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); |
| 58 | |
| 59 | /* SBE counter/threshold */ |
| 60 | printf("Memory Single-Bit Error Management (0..255):\n"); |
| 61 | printf(" Single-Bit Error Threshold: %d\n", |
| 62 | (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); |
| 63 | printf(" Single-Bit Error Counter: %d\n\n", |
| 64 | (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); |
| 65 | |
| 66 | /* Error detect */ |
| 67 | printf("Memory Error Detect:\n"); |
| 68 | printf(" Multiple Memory Errors: %d\n", |
| 69 | (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); |
| 70 | printf(" Multiple-Bit Error: %d\n", |
| 71 | (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); |
| 72 | printf(" Single-Bit Error: %d\n", |
| 73 | (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); |
| 74 | printf(" Memory Select Error: %d\n\n", |
| 75 | (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); |
| 76 | |
| 77 | /* Capture data */ |
Kim Phillips | f91aa8d | 2008-07-10 14:00:15 -0500 | [diff] [blame] | 78 | printf("Memory Error Address Capture: 0x%08x\n", ddr->capture_address); |
| 79 | printf("Memory Data Path Read Capture High/Low: %08x %08x\n", |
Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 80 | ddr->capture_data_hi, ddr->capture_data_lo); |
| 81 | printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", |
| 82 | ddr->capture_ecc & CAPTURE_ECC_ECE); |
| 83 | |
| 84 | printf("Memory Error Attributes Capture:\n"); |
| 85 | printf(" Data Beat Number: %d\n", |
| 86 | (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> |
| 87 | ECC_CAPT_ATTR_BNUM_SHIFT); |
| 88 | printf(" Transaction Size: %d\n", |
| 89 | (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> |
| 90 | ECC_CAPT_ATTR_TSIZ_SHIFT); |
| 91 | printf(" Transaction Source: %d\n", |
| 92 | (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> |
| 93 | ECC_CAPT_ATTR_TSRC_SHIFT); |
| 94 | printf(" Transaction Type: %d\n", |
| 95 | (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> |
| 96 | ECC_CAPT_ATTR_TTYP_SHIFT); |
| 97 | printf(" Error Information Valid: %d\n\n", |
| 98 | ddr->capture_attributes & ECC_CAPT_ATTR_VLD); |
| 99 | } |
| 100 | |
Wolfgang Denk | 6262d021 | 2010-06-28 22:00:46 +0200 | [diff] [blame] | 101 | int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 102 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 104 | volatile ddr83xx_t *ddr = &immap->ddr; |
| 105 | volatile u32 val; |
| 106 | u64 *addr; |
| 107 | u32 count; |
| 108 | register u64 *i; |
| 109 | u32 ret[2]; |
| 110 | u32 pattern[2]; |
| 111 | u32 writeback[2]; |
| 112 | |
| 113 | /* The pattern is written into memory to generate error */ |
| 114 | pattern[0] = 0xfedcba98UL; |
| 115 | pattern[1] = 0x76543210UL; |
| 116 | |
| 117 | /* After injecting error, re-initialize the memory with the value */ |
| 118 | writeback[0] = 0x01234567UL; |
| 119 | writeback[1] = 0x89abcdefUL; |
| 120 | |
| 121 | if (argc > 4) { |
Peter Tyser | ddb3af9 | 2009-01-27 18:03:10 -0600 | [diff] [blame] | 122 | cmd_usage(cmdtp); |
Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 123 | return 1; |
| 124 | } |
| 125 | |
| 126 | if (argc == 2) { |
| 127 | if (strcmp(argv[1], "status") == 0) { |
| 128 | ecc_print_status(); |
| 129 | return 0; |
| 130 | } else if (strcmp(argv[1], "captureclear") == 0) { |
| 131 | ddr->capture_address = 0; |
| 132 | ddr->capture_data_hi = 0; |
| 133 | ddr->capture_data_lo = 0; |
| 134 | ddr->capture_ecc = 0; |
| 135 | ddr->capture_attributes = 0; |
| 136 | return 0; |
| 137 | } |
| 138 | } |
| 139 | if (argc == 3) { |
| 140 | if (strcmp(argv[1], "sbecnt") == 0) { |
| 141 | val = simple_strtoul(argv[2], NULL, 10); |
| 142 | if (val > 255) { |
| 143 | printf("Incorrect Counter value, " |
| 144 | "should be 0..255\n"); |
| 145 | return 1; |
| 146 | } |
| 147 | |
| 148 | val = (val << ECC_ERROR_MAN_SBEC_SHIFT); |
| 149 | val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); |
| 150 | |
| 151 | ddr->err_sbe = val; |
| 152 | return 0; |
| 153 | } else if (strcmp(argv[1], "sbethr") == 0) { |
| 154 | val = simple_strtoul(argv[2], NULL, 10); |
| 155 | if (val > 255) { |
| 156 | printf("Incorrect Counter value, " |
| 157 | "should be 0..255\n"); |
| 158 | return 1; |
| 159 | } |
| 160 | |
| 161 | val = (val << ECC_ERROR_MAN_SBET_SHIFT); |
| 162 | val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); |
| 163 | |
| 164 | ddr->err_sbe = val; |
| 165 | return 0; |
| 166 | } else if (strcmp(argv[1], "errdisable") == 0) { |
| 167 | val = ddr->err_disable; |
| 168 | |
| 169 | if (strcmp(argv[2], "+sbe") == 0) { |
| 170 | val |= ECC_ERROR_DISABLE_SBED; |
| 171 | } else if (strcmp(argv[2], "+mbe") == 0) { |
| 172 | val |= ECC_ERROR_DISABLE_MBED; |
| 173 | } else if (strcmp(argv[2], "+mse") == 0) { |
| 174 | val |= ECC_ERROR_DISABLE_MSED; |
| 175 | } else if (strcmp(argv[2], "+all") == 0) { |
| 176 | val |= (ECC_ERROR_DISABLE_SBED | |
| 177 | ECC_ERROR_DISABLE_MBED | |
| 178 | ECC_ERROR_DISABLE_MSED); |
| 179 | } else if (strcmp(argv[2], "-sbe") == 0) { |
| 180 | val &= ~ECC_ERROR_DISABLE_SBED; |
| 181 | } else if (strcmp(argv[2], "-mbe") == 0) { |
| 182 | val &= ~ECC_ERROR_DISABLE_MBED; |
| 183 | } else if (strcmp(argv[2], "-mse") == 0) { |
| 184 | val &= ~ECC_ERROR_DISABLE_MSED; |
| 185 | } else if (strcmp(argv[2], "-all") == 0) { |
| 186 | val &= ~(ECC_ERROR_DISABLE_SBED | |
| 187 | ECC_ERROR_DISABLE_MBED | |
| 188 | ECC_ERROR_DISABLE_MSED); |
| 189 | } else { |
| 190 | printf("Incorrect err_disable field\n"); |
| 191 | return 1; |
| 192 | } |
| 193 | |
| 194 | ddr->err_disable = val; |
| 195 | __asm__ __volatile__("sync"); |
| 196 | __asm__ __volatile__("isync"); |
| 197 | return 0; |
| 198 | } else if (strcmp(argv[1], "errdetectclr") == 0) { |
| 199 | val = ddr->err_detect; |
| 200 | |
| 201 | if (strcmp(argv[2], "mme") == 0) { |
| 202 | val |= ECC_ERROR_DETECT_MME; |
| 203 | } else if (strcmp(argv[2], "sbe") == 0) { |
| 204 | val |= ECC_ERROR_DETECT_SBE; |
| 205 | } else if (strcmp(argv[2], "mbe") == 0) { |
| 206 | val |= ECC_ERROR_DETECT_MBE; |
| 207 | } else if (strcmp(argv[2], "mse") == 0) { |
| 208 | val |= ECC_ERROR_DETECT_MSE; |
| 209 | } else if (strcmp(argv[2], "all") == 0) { |
| 210 | val |= (ECC_ERROR_DETECT_MME | |
| 211 | ECC_ERROR_DETECT_MBE | |
| 212 | ECC_ERROR_DETECT_SBE | |
| 213 | ECC_ERROR_DETECT_MSE); |
| 214 | } else { |
| 215 | printf("Incorrect err_detect field\n"); |
| 216 | return 1; |
| 217 | } |
| 218 | |
| 219 | ddr->err_detect = val; |
| 220 | return 0; |
| 221 | } else if (strcmp(argv[1], "injectdatahi") == 0) { |
| 222 | val = simple_strtoul(argv[2], NULL, 16); |
| 223 | |
| 224 | ddr->data_err_inject_hi = val; |
| 225 | return 0; |
| 226 | } else if (strcmp(argv[1], "injectdatalo") == 0) { |
| 227 | val = simple_strtoul(argv[2], NULL, 16); |
| 228 | |
| 229 | ddr->data_err_inject_lo = val; |
| 230 | return 0; |
| 231 | } else if (strcmp(argv[1], "injectecc") == 0) { |
| 232 | val = simple_strtoul(argv[2], NULL, 16); |
| 233 | if (val > 0xff) { |
| 234 | printf("Incorrect ECC inject mask, " |
| 235 | "should be 0x00..0xff\n"); |
| 236 | return 1; |
| 237 | } |
| 238 | val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); |
| 239 | |
| 240 | ddr->ecc_err_inject = val; |
| 241 | return 0; |
| 242 | } else if (strcmp(argv[1], "inject") == 0) { |
| 243 | val = ddr->ecc_err_inject; |
| 244 | |
| 245 | if (strcmp(argv[2], "en") == 0) |
| 246 | val |= ECC_ERR_INJECT_EIEN; |
| 247 | else if (strcmp(argv[2], "dis") == 0) |
| 248 | val &= ~ECC_ERR_INJECT_EIEN; |
| 249 | else |
| 250 | printf("Incorrect command\n"); |
| 251 | |
| 252 | ddr->ecc_err_inject = val; |
| 253 | __asm__ __volatile__("sync"); |
| 254 | __asm__ __volatile__("isync"); |
| 255 | return 0; |
| 256 | } else if (strcmp(argv[1], "mirror") == 0) { |
| 257 | val = ddr->ecc_err_inject; |
| 258 | |
| 259 | if (strcmp(argv[2], "en") == 0) |
| 260 | val |= ECC_ERR_INJECT_EMB; |
| 261 | else if (strcmp(argv[2], "dis") == 0) |
| 262 | val &= ~ECC_ERR_INJECT_EMB; |
| 263 | else |
| 264 | printf("Incorrect command\n"); |
| 265 | |
| 266 | ddr->ecc_err_inject = val; |
| 267 | return 0; |
| 268 | } |
| 269 | } |
| 270 | if (argc == 4) { |
| 271 | if (strcmp(argv[1], "testdw") == 0) { |
| 272 | addr = (u64 *) simple_strtoul(argv[2], NULL, 16); |
| 273 | count = simple_strtoul(argv[3], NULL, 16); |
| 274 | |
| 275 | if ((u32) addr % 8) { |
| 276 | printf("Address not alligned on " |
| 277 | "double word boundary\n"); |
| 278 | return 1; |
| 279 | } |
| 280 | disable_interrupts(); |
| 281 | |
| 282 | for (i = addr; i < addr + count; i++) { |
| 283 | |
| 284 | /* enable injects */ |
| 285 | ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; |
| 286 | __asm__ __volatile__("sync"); |
| 287 | __asm__ __volatile__("isync"); |
| 288 | |
| 289 | /* write memory location injecting errors */ |
| 290 | ppcDWstore((u32 *) i, pattern); |
| 291 | __asm__ __volatile__("sync"); |
| 292 | |
| 293 | /* disable injects */ |
| 294 | ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; |
| 295 | __asm__ __volatile__("sync"); |
| 296 | __asm__ __volatile__("isync"); |
| 297 | |
| 298 | /* read data, this generates ECC error */ |
| 299 | ppcDWload((u32 *) i, ret); |
| 300 | __asm__ __volatile__("sync"); |
| 301 | |
| 302 | /* re-initialize memory, double word write the location again, |
| 303 | * generates new ECC code this time */ |
| 304 | ppcDWstore((u32 *) i, writeback); |
| 305 | __asm__ __volatile__("sync"); |
| 306 | } |
| 307 | enable_interrupts(); |
| 308 | return 0; |
| 309 | } |
| 310 | if (strcmp(argv[1], "testword") == 0) { |
| 311 | addr = (u64 *) simple_strtoul(argv[2], NULL, 16); |
| 312 | count = simple_strtoul(argv[3], NULL, 16); |
| 313 | |
| 314 | if ((u32) addr % 8) { |
| 315 | printf("Address not alligned on " |
| 316 | "double word boundary\n"); |
| 317 | return 1; |
| 318 | } |
| 319 | disable_interrupts(); |
| 320 | |
| 321 | for (i = addr; i < addr + count; i++) { |
| 322 | |
| 323 | /* enable injects */ |
| 324 | ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; |
| 325 | __asm__ __volatile__("sync"); |
| 326 | __asm__ __volatile__("isync"); |
| 327 | |
| 328 | /* write memory location injecting errors */ |
| 329 | *(u32 *) i = 0xfedcba98UL; |
| 330 | __asm__ __volatile__("sync"); |
| 331 | |
| 332 | /* sub double word write, |
| 333 | * bus will read-modify-write, |
| 334 | * generates ECC error */ |
| 335 | *((u32 *) i + 1) = 0x76543210UL; |
| 336 | __asm__ __volatile__("sync"); |
| 337 | |
| 338 | /* disable injects */ |
| 339 | ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; |
| 340 | __asm__ __volatile__("sync"); |
| 341 | __asm__ __volatile__("isync"); |
| 342 | |
| 343 | /* re-initialize memory, |
| 344 | * double word write the location again, |
| 345 | * generates new ECC code this time */ |
| 346 | ppcDWstore((u32 *) i, writeback); |
| 347 | __asm__ __volatile__("sync"); |
| 348 | } |
| 349 | enable_interrupts(); |
| 350 | return 0; |
| 351 | } |
| 352 | } |
Peter Tyser | ddb3af9 | 2009-01-27 18:03:10 -0600 | [diff] [blame] | 353 | cmd_usage(cmdtp); |
Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 354 | return 1; |
| 355 | } |
| 356 | |
| 357 | U_BOOT_CMD(ecc, 4, 0, do_ecc, |
Peter Tyser | dfb72b8 | 2009-01-27 18:03:12 -0600 | [diff] [blame] | 358 | "support for DDR ECC features", |
Dave Liu | a2c2ceb | 2007-08-01 15:00:15 +0800 | [diff] [blame] | 359 | "status - print out status info\n" |
| 360 | "ecc captureclear - clear capture regs data\n" |
| 361 | "ecc sbecnt <val> - set Single-Bit Error counter\n" |
| 362 | "ecc sbethr <val> - set Single-Bit Threshold\n" |
| 363 | "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n" |
| 364 | " [-|+]sbe - Single-Bit Error\n" |
| 365 | " [-|+]mbe - Multiple-Bit Error\n" |
| 366 | " [-|+]mse - Memory Select Error\n" |
| 367 | " [-|+]all - all errors\n" |
| 368 | "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n" |
| 369 | " mme - Multiple Memory Errors\n" |
| 370 | " sbe - Single-Bit Error\n" |
| 371 | " mbe - Multiple-Bit Error\n" |
| 372 | " mse - Memory Select Error\n" |
| 373 | " all - all errors\n" |
| 374 | "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n" |
| 375 | "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n" |
| 376 | "ecc injectecc <ecc> - set ECC Error Injection Mask\n" |
| 377 | "ecc inject <en|dis> - enable/disable error injection\n" |
| 378 | "ecc mirror <en|dis> - enable/disable mirror byte\n" |
| 379 | "ecc testdw <addr> <cnt> - test mem region with double word access:\n" |
| 380 | " - enables injects\n" |
| 381 | " - writes pattern injecting errors with double word access\n" |
| 382 | " - disables injects\n" |
| 383 | " - reads pattern back with double word access, generates error\n" |
| 384 | " - re-inits memory\n" |
| 385 | "ecc testword <addr> <cnt> - test mem region with word access:\n" |
| 386 | " - enables injects\n" |
| 387 | " - writes pattern injecting errors with word access\n" |
| 388 | " - writes pattern with word access, generates error\n" |
| 389 | " - disables injects\n" " - re-inits memory"); |
| 390 | #endif |