| Marek Vasut | a3fb96c | 2014-12-30 21:08:57 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Altera Corporation <www.altera.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | /* First 4KB has trampoline code for secondary cores. */ |
| 9 | /memreserve/ 0x00000000 0x0001000; |
| 10 | #include "socfpga.dtsi" |
| 11 | |
| 12 | / { |
| 13 | soc { |
| 14 | clkmgr@ffd04000 { |
| 15 | clocks { |
| 16 | osc1 { |
| 17 | clock-frequency = <25000000>; |
| 18 | }; |
| 19 | }; |
| 20 | }; |
| 21 | |
| 22 | mmc0: dwmmc0@ff704000 { |
| 23 | num-slots = <1>; |
| 24 | broken-cd; |
| 25 | bus-width = <4>; |
| 26 | cap-mmc-highspeed; |
| 27 | cap-sd-highspeed; |
| Chin Liang See | d6391a8 | 2015-11-26 09:44:11 +0800 | [diff] [blame] | 28 | drvsel = <3>; |
| 29 | smplsel = <0>; |
| Marek Vasut | a3fb96c | 2014-12-30 21:08:57 +0100 | [diff] [blame] | 30 | }; |
| 31 | |
| 32 | sysmgr@ffd08000 { |
| 33 | cpu1-start-addr = <0xffd080c4>; |
| 34 | }; |
| 35 | }; |
| 36 | }; |