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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard1e1d02d2017-09-13 18:00:12 +02002/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
Patrice Chotard5d9950d2020-12-02 18:47:30 +01004 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotard1e1d02d2017-09-13 18:00:12 +02005 */
6
7#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Patrice Chotard1e1d02d2017-09-13 18:00:12 +02009#include <asm/io.h>
Lokesh Vutla076ee452018-04-26 18:21:30 +053010#include <asm/armv7_mpu.h>
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020011
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020012int arch_cpu_init(void)
13{
14 int i;
15
16 struct mpu_region_config stm32_region_config[] = {
17 /*
Patrice Chotard574f4572018-02-28 17:15:00 +010018 * Make SDRAM area cacheable & executable.
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020019 */
Patrice Chotard574f4572018-02-28 17:15:00 +010020#if defined(CONFIG_STM32F4)
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020021 { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
Patrice Chotard832f3ed2019-06-25 13:24:03 +020022 O_I_WB_RD_WR_ALLOC, REGION_512MB },
Patrice Chotard574f4572018-02-28 17:15:00 +010023#endif
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020024
Patrice Chotardbb1a5502019-04-26 10:52:51 +020025 { 0x90000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
26 SHARED_WRITE_BUFFERED, REGION_256MB },
27
Patrice Chotard67030742018-10-02 09:03:10 +020028#if defined(CONFIG_STM32F7) || defined(CONFIG_STM32H7)
Patrice Chotard574f4572018-02-28 17:15:00 +010029 { 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
Patrice Chotard67030742018-10-02 09:03:10 +020030 O_I_WB_RD_WR_ALLOC, REGION_512MB },
Patrice Chotard0c6247c2017-11-16 08:59:21 +010031#endif
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020032 };
33
34 disable_mpu();
35 for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
36 mpu_config(&stm32_region_config[i]);
37 enable_mpu();
38
39 return 0;
40}