| Hans de Goede | 35e1a15 | 2015-01-14 17:30:22 +0100 | [diff] [blame] | 1 | /* |
| 2 | * sun9i clock register definitions |
| 3 | * |
| 4 | * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef _SUNXI_CLOCK_SUN9I_H |
| 10 | #define _SUNXI_CLOCK_SUN9I_H |
| 11 | |
| 12 | struct sunxi_ccm_reg { |
| 13 | u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ |
| 14 | u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ |
| 15 | u32 pll3_audio_cfg; /* 0x08 audio pll configuration */ |
| 16 | u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */ |
| 17 | u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */ |
| 18 | u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */ |
| 19 | u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */ |
| 20 | u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */ |
| 21 | u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */ |
| 22 | u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */ |
| 23 | u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */ |
| 24 | u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */ |
| 25 | u8 reserved1[0x20]; /* 0x30 */ |
| 26 | u32 cpu_clk_source; /* 0x50 cpu clk source configuration */ |
| 27 | u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */ |
| 28 | u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */ |
| 29 | u32 gtbus_cfg; /* 0x5c gtbus clock configuration */ |
| 30 | u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */ |
| 31 | u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */ |
| 32 | u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */ |
| 33 | u8 reserved2[0x04]; /* 0x6c */ |
| 34 | u32 apb0_cfg; /* 0x70 apb0 clock configuration */ |
| 35 | u32 apb1_cfg; /* 0x74 apb1 clock configuration */ |
| 36 | u32 cci400_cfg; /* 0x78 cci400 clock configuration */ |
| 37 | u8 reserved3[0x04]; /* 0x7c */ |
| 38 | u32 ats_cfg; /* 0x80 ats clock configuration */ |
| 39 | u32 trace_cfg; /* 0x84 trace clock configuration */ |
| 40 | u8 reserved4[0xf8]; /* 0x88 */ |
| 41 | u32 clk_output_a; /* 0x180 clk_output_a */ |
| 42 | u32 clk_output_b; /* 0x184 clk_output_a */ |
| 43 | u8 reserved5[0x278]; /* 0x188 */ |
| 44 | |
| 45 | u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */ |
| 46 | u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */ |
| 47 | u8 reserved6[0x08]; /* 0x408 */ |
| 48 | u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */ |
| 49 | u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */ |
| 50 | u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */ |
| 51 | u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */ |
| 52 | u8 reserved7[0x08]; /* 0x420 */ |
| 53 | u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */ |
| 54 | u32 ss_clk_cfg; /* 0x42c security system clock cfg */ |
| 55 | u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */ |
| 56 | u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */ |
| 57 | u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */ |
| 58 | u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */ |
| 59 | u8 reserved8[0x50]; /* 0x440 */ |
| 60 | u32 de_clk_cfg; /* 0x490 display engine clock configuration */ |
| 61 | u8 reserved9[0x04]; /* 0x494 */ |
| 62 | u32 mp_clk_cfg; /* 0x498 mp clock configuration */ |
| 63 | u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */ |
| 64 | u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */ |
| 65 | u8 reserved10[0x1c]; /* 0x4a4 */ |
| 66 | u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */ |
| 67 | u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */ |
| 68 | u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */ |
| 69 | u32 fd_clk_cfg; /* 0x4cc FD module clock */ |
| 70 | u32 ve_clk_cfg; /* 0x4d0 VE module clock */ |
| 71 | u32 avs_clk_cfg; /* 0x4d4 AVS module clock */ |
| 72 | u8 reserved11[0x18]; /* 0x4d8 */ |
| 73 | u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */ |
| 74 | u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */ |
| 75 | u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */ |
| 76 | u8 reserved12[0x10]; /* 0x4fc */ |
| 77 | u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */ |
| 78 | u8 reserved13[0x70]; /* 0x510 */ |
| 79 | |
| 80 | u32 ahb_gate0; /* 0x580 AHB0 Gating Register */ |
| 81 | u32 ahb_gate1; /* 0x584 AHB1 Gating Register */ |
| 82 | u32 ahb_gate2; /* 0x588 AHB2 Gating Register */ |
| 83 | u8 reserved14[0x04]; /* 0x58c */ |
| 84 | u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */ |
| 85 | u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */ |
| 86 | u8 reserved15[0x08]; /* 0x598 */ |
| 87 | u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */ |
| 88 | u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ |
| 89 | u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */ |
| 90 | u8 reserved16[0x04]; /* 0x5ac */ |
| 91 | u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */ |
| 92 | u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ |
| 93 | }; |
| 94 | |
| 95 | /* pll4_periph0_cfg */ |
| 96 | #define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */ |
| 97 | |
| 98 | #define CCM_PLL4_CTRL_N_SHIFT 8 |
| 99 | #define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT) |
| 100 | #define CCM_PLL4_CTRL_P_SHIFT 16 |
| 101 | #define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT) |
| 102 | #define CCM_PLL4_CTRL_M_SHIFT 18 |
| 103 | #define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT) |
| 104 | |
| 105 | /* sd#_clk_cfg fields */ |
| 106 | #define CCM_MMC_CTRL_M(x) ((x) - 1) |
| 107 | #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) |
| 108 | #define CCM_MMC_CTRL_N(x) ((x) << 16) |
| 109 | #define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) |
| 110 | #define CCM_MMC_CTRL_OSCM24 (0 << 24) |
| 111 | #define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24) |
| 112 | #define CCM_MMC_CTRL_ENABLE (1 << 31) |
| 113 | |
| 114 | /* ahb_gate0 fields */ |
| 115 | /* On sun9i all sdc-s share their ahb gate, so ignore (x) */ |
| 116 | #define AHB_GATE_OFFSET_MMC(x) 8 |
| 117 | |
| 118 | /* apb1_gate fields */ |
| 119 | #define APB1_GATE_UART_SHIFT 16 |
| 120 | #define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) |
| 121 | #define APB1_GATE_TWI_SHIFT 0 |
| 122 | #define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) |
| 123 | |
| 124 | /* ahb_reset0_cfg fields */ |
| 125 | /* On sun9i all sdc-s share their ahb reset, so ignore (x) */ |
| 126 | #define AHB_RESET_OFFSET_MMC(x) 8 |
| 127 | |
| 128 | /* apb1_reset_cfg fields */ |
| 129 | #define APB1_RESET_UART_SHIFT 16 |
| 130 | #define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT) |
| 131 | #define APB1_RESET_TWI_SHIFT 0 |
| 132 | #define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) |
| 133 | |
| 134 | |
| 135 | #ifndef __ASSEMBLY__ |
| 136 | unsigned int clock_get_pll4_periph0(void); |
| 137 | #endif |
| 138 | |
| 139 | #endif /* _SUNXI_CLOCK_SUN9I_H */ |