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git01.mediatek.com / filogic / uboot / 6cf2ddb5f094a9dfa6d035b5f11bd7ed43136c6e / . / arch / arm / include / asm / arch-rockchip / hdmi_rk3288.h
blob: 0b51d40882b65e867766f834e53b9921b85469af [file] [log] [blame]
Simon Glass0139ae62016-01-21 19:45:03 -0700[diff] [blame]1/*
2 * Copyright (c) 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
4 * Copyright (C) 2011 Freescale Semiconductor, Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef _ASM_ARCH_HDMI_H
10#define _ASM_ARCH_HDMI_H
11
12
13#define HDMI_EDID_BLOCK_SIZE 128
14
15struct rk3288_hdmi {
16 u32 reserved0[0x100];
17 u32 ih_fc_stat0;
18 u32 ih_fc_stat1;
19 u32 ih_fc_stat2;
20 u32 ih_as_stat0;
21 u32 ih_phy_stat0;
22 u32 ih_i2cm_stat0;
23 u32 ih_cec_stat0;
24 u32 ih_vp_stat0;
25 u32 ih_i2cmphy_stat0;
26 u32 ih_ahbdmaaud_stat0;
27 u32 reserved1[0x17f-0x109];
28 u32 ih_mute_fc_stat0;
29 u32 ih_mute_fc_stat1;
30 u32 ih_mute_fc_stat2;
31 u32 ih_mute_as_stat0;
32 u32 ih_mute_phy_stat0;
33 u32 ih_mute_i2cm_stat0;
34 u32 ih_mute_cec_stat0;
35 u32 ih_mute_vp_stat0;
36 u32 ih_mute_i2cmphy_stat0;
37 u32 ih_mute_ahbdmaaud_stat0;
38 u32 reserved2[0x1fe - 0x189];
39 u32 ih_mute;
40 u32 tx_invid0;
41 u32 tx_instuffing;
42 u32 tx_gydata0;
43 u32 tx_gydata1;
44 u32 tx_rcrdata0;
45 u32 tx_rcrdata1;
46 u32 tx_bcbdata0;
47 u32 tx_bcbdata1;
48 u32 reserved3[0x7ff-0x207];
49 u32 vp_status;
50 u32 vp_pr_cd;
51 u32 vp_stuff;
52 u32 vp_remap;
53 u32 vp_conf;
54 u32 vp_stat;
55 u32 vp_int;
56 u32 vp_mask;
57 u32 vp_pol;
58 u32 reserved4[0xfff-0x808];
59 u32 fc_invidconf;
60 u32 fc_inhactv0;
61 u32 fc_inhactv1;
62 u32 fc_inhblank0;
63 u32 fc_inhblank1;
64 u32 fc_invactv0;
65 u32 fc_invactv1;
66 u32 fc_invblank;
67 u32 fc_hsyncindelay0;
68 u32 fc_hsyncindelay1;
69 u32 fc_hsyncinwidth0;
70 u32 fc_hsyncinwidth1;
71 u32 fc_vsyncindelay;
72 u32 fc_vsyncinwidth;
73 u32 fc_infreq0;
74 u32 fc_infreq1;
75 u32 fc_infreq2;
76 u32 fc_ctrldur;
77 u32 fc_exctrldur;
78 u32 fc_exctrlspac;
79 u32 fc_ch0pream;
80 u32 fc_ch1pream;
81 u32 fc_ch2pream;
82 u32 fc_aviconf3;
83 u32 fc_gcp;
84 u32 fc_aviconf0;
85 u32 fc_aviconf1;
86 u32 fc_aviconf2;
87 u32 fc_avivid;
88 u32 fc_avietb0;
89 u32 fc_avietb1;
90 u32 fc_avisbb0;
91 u32 fc_avisbb1;
92 u32 fc_avielb0;
93 u32 fc_avielb1;
94 u32 fc_avisrb0;
95 u32 fc_avisrb1;
96 u32 fc_audiconf0;
97 u32 fc_audiconf1;
98 u32 fc_audiconf2;
99 u32 fc_audiconf3;
100 u32 fc_vsdieeeid0;
101 u32 fc_vsdsize;
102 u32 reserved7[0x2fff-0x102a];
103 u32 phy_conf0;
104 u32 phy_tst0;
105 u32 phy_tst1;
106 u32 phy_tst2;
107 u32 phy_stat0;
108 u32 phy_int0;
109 u32 phy_mask0;
110 u32 phy_pol0;
111 u32 reserved8[0x301f-0x3007];
112 u32 phy_i2cm_slave_addr;
113 u32 phy_i2cm_address_addr;
114 u32 phy_i2cm_datao_1_addr;
115 u32 phy_i2cm_datao_0_addr;
116 u32 phy_i2cm_datai_1_addr;
117 u32 phy_i2cm_datai_0_addr;
118 u32 phy_i2cm_operation_addr;
119 u32 phy_i2cm_int_addr;
120 u32 phy_i2cm_ctlint_addr;
121 u32 phy_i2cm_div_addr;
122 u32 phy_i2cm_softrstz_addr;
123 u32 phy_i2cm_ss_scl_hcnt_1_addr;
124 u32 phy_i2cm_ss_scl_hcnt_0_addr;
125 u32 phy_i2cm_ss_scl_lcnt_1_addr;
126 u32 phy_i2cm_ss_scl_lcnt_0_addr;
127 u32 phy_i2cm_fs_scl_hcnt_1_addr;
128 u32 phy_i2cm_fs_scl_hcnt_0_addr;
129 u32 phy_i2cm_fs_scl_lcnt_1_addr;
130 u32 phy_i2cm_fs_scl_lcnt_0_addr;
131 u32 reserved9[0x30ff-0x3032];
132 u32 aud_conf0;
133 u32 aud_conf1;
134 u32 aud_int;
135 u32 aud_conf2;
136 u32 aud_int1;
137 u32 reserved32[0x31ff-0x3104];
138 u32 aud_n1;
139 u32 aud_n2;
140 u32 aud_n3;
141 u32 aud_cts1;
142 u32 aud_cts2;
143 u32 aud_cts3;
144 u32 aud_inputclkfs;
145 u32 reserved12[0x3fff-0x3206];
146 u32 mc_sfrdiv;
147 u32 mc_clkdis;
148 u32 mc_swrstz;
149 u32 mc_opctrl;
150 u32 mc_flowctrl;
151 u32 mc_phyrstz;
152 u32 mc_lockonclock;
153 u32 mc_heacphy_rst;
154 u32 reserved13[0x40ff-0x4007];
155 u32 csc_cfg;
156 u32 csc_scale;
157 struct {
158 u32 msb;
159 u32 lsb;
160 } csc_coef[3][4];
161 u32 reserved17[0x7dff-0x4119];
162 u32 i2cm_slave;
163 u32 i2c_address;
164 u32 i2cm_datao;
165 u32 i2cm_datai;
166 u32 i2cm_operation;
167 u32 i2cm_int;
168 u32 i2cm_ctlint;
169 u32 i2cm_div;
170 u32 i2cm_segaddr;
171 u32 i2cm_softrstz;
172 u32 i2cm_segptr;
173 u32 i2cm_ss_scl_hcnt_1_addr;
174 u32 i2cm_ss_scl_hcnt_0_addr;
175 u32 i2cm_ss_scl_lcnt_1_addr;
176 u32 i2cm_ss_scl_lcnt_0_addr;
177 u32 i2cm_fs_scl_hcnt_1_addr;
178 u32 i2cm_fs_scl_hcnt_0_addr;
179 u32 i2cm_fs_scl_lcnt_1_addr;
180 u32 i2cm_fs_scl_lcnt_0_addr;
181 u32 reserved18[0x7e1f-0x7e12];
182 u32 i2cm_buf0;
183};
184check_member(rk3288_hdmi, i2cm_buf0, 0x1f880);
185
186enum {
187 /* HDMI PHY registers define */
188 PHY_OPMODE_PLLCFG = 0x06,
189 PHY_CKCALCTRL = 0x05,
190 PHY_CKSYMTXCTRL = 0x09,
191 PHY_VLEVCTRL = 0x0e,
192 PHY_PLLCURRCTRL = 0x10,
193 PHY_PLLPHBYCTRL = 0x13,
194 PHY_PLLGMPCTRL = 0x15,
195 PHY_PLLCLKBISTPHASE = 0x17,
196 PHY_TXTERM = 0x19,
197
198 /* ih_phy_stat0 field values */
199 HDMI_IH_PHY_STAT0_HPD = 0x1,
200
201 /* ih_mute field values */
202 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
203 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
204
205 /* tx_invid0 field values */
206 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
207 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
208 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
209
210 /* tx_instuffing field values */
211 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
212 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
213 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
214
215 /* vp_pr_cd field values */
216 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
217 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
218 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
219 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
220
221 /* vp_stuff field values */
222 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
223 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
224 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
225 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
226 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
227 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
228 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
229 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
230
231 /* vp_conf field values */
232 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
233 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
234 HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
235 HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
236 HDMI_VP_CONF_PR_EN_MASK = 0x10,
237 HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
238 HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
239 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
240 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
241 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
242 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
243 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
244
245 /* vp_remap field values */
246 HDMI_VP_REMAP_YCC422_16BIT = 0x0,
247
248 /* fc_invidconf field values */
249 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
250 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
251 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
252 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
253 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
254 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
255 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
256 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
257 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
258 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
259 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
260 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
261 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
262 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
263 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
264 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
265 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
266 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
267 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
268 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
269 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
270
271
272 /* fc_aviconf0-fc_aviconf3 field values */
273 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
274 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
275 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
276 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
277 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
278 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
279 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
280 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
281 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
282 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
283 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
284 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
285 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
286 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
287 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
288 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
289
290 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
291 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
292 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
293 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
294 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
295 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
296 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
297 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
298 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
299 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
300 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
301 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
302 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
303 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
304
305 HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
306 HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
307 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
308 HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
309 HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
310 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
311 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
312 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
313 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
314 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
315 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
316 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
317 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
318 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
319 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
320 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
321 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
322 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
323
324 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
325 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
326 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
327 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
328 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
329 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
330 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
331 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
332
333 /* fc_gcp field values*/
334 HDMI_FC_GCP_SET_AVMUTE = 0x02,
335 HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
336
337 /* phy_conf0 field values */
338 HDMI_PHY_CONF0_PDZ_MASK = 0x80,
339 HDMI_PHY_CONF0_PDZ_OFFSET = 7,
340 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
341 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
342 HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
343 HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
344 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
345 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
346 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
347 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
348 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
349 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
350 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
351 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
352
353 /* phy_tst0 field values */
354 HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
355 HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
356
357 /* phy_stat0 field values */
358 HDMI_PHY_HPD = 0x02,
359 HDMI_PHY_TX_PHY_LOCK = 0x01,
360
361 /* phy_i2cm_slave_addr field values */
362 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
363
364 /* phy_i2cm_operation_addr field values */
365 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
366
367 /* hdmi_phy_i2cm_int_addr */
368 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
369
370 /* hdmi_phy_i2cm_ctlint_addr */
371 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
372 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
373
374 /* aud_conf0 field values */
375 HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
376 HDMI_AUD_CONF0_I2S_SELECT = 0x20,
377 HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
378 HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
379 HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
380 HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
381
382 /* aud_conf0 field values */
383 HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
384 HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
385
386 /* aud_n3 field values */
387 HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
388 HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
389
390 /* aud_cts3 field values */
391 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
392 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
393 HDMI_AUD_CTS3_N_SHIFT_1 = 0,
394 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
395 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
396 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
397 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
398 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
399 HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
400 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
401
402 /* aud_inputclkfs filed values */
403 HDMI_AUD_INPUTCLKFS_128 = 0x0,
404
405 /* mc_clkdis field values */
406 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
407 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
408 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
409
410 /* mc_swrstz field values */
411 HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
412 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
413
414 /* mc_flowctrl field values */
415 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
416 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
417
418 /* mc_phyrstz field values */
419 HDMI_MC_PHYRSTZ_ASSERT = 0x0,
420 HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
421
422 /* mc_heacphy_rst field values */
423 HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
424
425 /* csc_cfg field values */
426 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
427
428 /* csc_scale field values */
429 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0,
430 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
431 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
432 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
433 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
434 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
435
436 /* i2cm filed values */
437 HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
438 HDMI_I2CM_SEGADDR_DDC = 0x30,
439 HDMI_I2CM_OPT_RD8_EXT = 0x8,
440 HDMI_I2CM_OPT_RD8 = 0x4,
441 HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
442 HDMI_I2CM_DIV_FAST_MODE = 0x8,
443 HDMI_I2CM_DIV_STD_MODE = 0x0,
444 HDMI_I2CM_SOFTRSTZ = 0x1,
445};
446
447/*
448struct display_timing;
449struct rk3288_grf;
450
451int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id);
452int rk_hdmi_enable(const struct display_timing *edid);
453int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing *edid);
454*/
455
456#endif