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Stefan Roese9b1e2312014-10-22 12:13:19 +02001/*
2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _CONFIG_DB_MV7846MP_GP_H
8#define _CONFIG_DB_MV7846MP_GP_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
Stefan Roese9b1e2312014-10-22 12:13:19 +020013#define CONFIG_DISPLAY_BOARDINFO_LATE
14
Stefan Roese3dbf35c2015-08-06 14:27:36 +020015/*
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
18 * U-Boot into it.
19 */
20#define CONFIG_SYS_TEXT_BASE 0x00800000
Stefan Roese9b1e2312014-10-22 12:13:19 +020021#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
22
23/*
24 * Commands configuration
25 */
Stefan Roese9b1e2312014-10-22 12:13:19 +020026
27/* I2C */
28#define CONFIG_SYS_I2C
29#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowski2fae3e72015-04-10 23:09:51 +020030#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese9b1e2312014-10-22 12:13:19 +020031#define CONFIG_SYS_I2C_SLAVE 0x0
32#define CONFIG_SYS_I2C_SPEED 100000
33
34/* SPI NOR flash default params, used by sf commands */
35#define CONFIG_SF_DEFAULT_SPEED 1000000
36#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Stefan Roese9b1e2312014-10-22 12:13:19 +020037
38/* Environment in SPI NOR flash */
39#define CONFIG_ENV_IS_IN_SPI_FLASH
40#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
41#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
42#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
43
44#define CONFIG_PHY_MARVELL /* there is a marvell phy */
Stefan Roese9b1e2312014-10-22 12:13:19 +020045#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
Stefan Roese9b1e2312014-10-22 12:13:19 +020046
Stefan Roese9b1e2312014-10-22 12:13:19 +020047#define CONFIG_SYS_ALT_MEMTEST
48
49/*
50 * mv-common.h should be defined after CMD configs since it used them
51 * to enable certain macros
52 */
53#include "mv-common.h"
54
Stefan Roese1a16a0c2015-01-19 11:33:47 +010055/*
56 * Memory layout while starting into the bin_hdr via the
57 * BootROM:
58 *
59 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
60 * 0x4000.4030 bin_hdr start address
61 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
62 * 0x4007.fffc BootROM stack top
63 *
64 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
65 * L2 cache thus cannot be used.
66 */
67
68/* SPL */
69/* Defines for SPL */
70#define CONFIG_SPL_FRAMEWORK
71#define CONFIG_SPL_TEXT_BASE 0x40004030
72#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
73
74#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
75#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
76
Stefan Roese83097cf2015-11-25 07:37:00 +010077#ifdef CONFIG_SPL_BUILD
78#define CONFIG_SYS_MALLOC_SIMPLE
79#endif
Stefan Roese1a16a0c2015-01-19 11:33:47 +010080
81#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
82#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
83
Stefan Roese1a16a0c2015-01-19 11:33:47 +010084/* SPL related SPI defines */
Stefan Roese1a16a0c2015-01-19 11:33:47 +010085#define CONFIG_SPL_SPI_LOAD
Stefan Roese1a16a0c2015-01-19 11:33:47 +010086#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
87
88/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roese1a16a0c2015-01-19 11:33:47 +010089#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
Stefan Roeseff7ad172015-12-10 15:02:38 +010090#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
Stefan Roese1a16a0c2015-01-19 11:33:47 +010091
Stefan Roese9b1e2312014-10-22 12:13:19 +020092#endif /* _CONFIG_DB_MV7846MP_GP_H */