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Wolfgang Denk52744b42013-07-28 22:12:45 +02001/*
Wolfgang Denk815c9672013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk52744b42013-07-28 22:12:45 +02003 */
wdenkc6097192002-11-03 00:24:07 +00004/*
5 * Adapted for PIP405 03.07.01
6 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
7 *
8 * TODO: Clean-up
9 */
10
11#include <common.h>
12#include <pci.h>
13#include "isa.h"
14
15#ifdef CONFIG_405GP
16#ifdef CONFIG_PCI
17
Wolfgang Denk6405a152006-03-31 18:32:53 +020018DECLARE_GLOBAL_DATA_PTR;
wdenkc6097192002-11-03 00:24:07 +000019
20#include "piix4_pci.h"
21#include "pci_parts.h"
22
Chakra Divia1fef712017-06-05 23:09:30 +053023void pci_405gp_init(struct pci_controller *hose);
24
wdenkc6097192002-11-03 00:24:07 +000025void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
Chakra Divia1fef712017-06-05 23:09:30 +053026 struct pci_config_table *entry)
wdenkc6097192002-11-03 00:24:07 +000027{
28 struct pci_pip405_config_entry *table;
29 int i;
30
Chakra Divia1fef712017-06-05 23:09:30 +053031 table = (struct pci_pip405_config_entry *)entry->priv[0];
wdenkc6097192002-11-03 00:24:07 +000032
Chakra Divia1fef712017-06-05 23:09:30 +053033 for (i = 0; table[i].width; i++) {
wdenkc6097192002-11-03 00:24:07 +000034#ifdef DEBUG
35 printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
36 table[i].index, table[i].val, table[i].width);
37#endif
38
Chakra Divia1fef712017-06-05 23:09:30 +053039 switch (table[i].width) {
40 case 1:
41 pci_hose_write_config_byte(hose, dev,
42 table[i].index, table[i].val);
43 break;
44 case 2:
45 pci_hose_write_config_word(hose, dev,
46 table[i].index, table[i].val);
47 break;
48 case 4:
49 pci_hose_write_config_dword(hose, dev,
50 table[i].index, table[i].val);
51 break;
wdenkc6097192002-11-03 00:24:07 +000052 }
53 }
54}
55
56
57static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
58{
59 unsigned char int_line = 0xff;
wdenkb02744a2003-04-05 00:53:31 +000060 unsigned char pin;
wdenkc6097192002-11-03 00:24:07 +000061 /*
62 * Write pci interrupt line register
63 */
Chakra Divia1fef712017-06-05 23:09:30 +053064 if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */
wdenkc6097192002-11-03 00:24:07 +000065 return;
wdenkb02744a2003-04-05 00:53:31 +000066 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
67 if ((pin == 0) || (pin > 4))
Chakra Divia1fef712017-06-05 23:09:30 +053068 return;
wdenkb02744a2003-04-05 00:53:31 +000069
70 int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
71 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
wdenkc6097192002-11-03 00:24:07 +000072#ifdef DEBUG
wdenkb02744a2003-04-05 00:53:31 +000073 printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
Chakra Divia1fef712017-06-05 23:09:30 +053074 PCI_DEV(dev), dev, int_line, int_line);
wdenkc6097192002-11-03 00:24:07 +000075#endif
wdenkc6097192002-11-03 00:24:07 +000076}
77
wdenkc6097192002-11-03 00:24:07 +000078
79static struct pci_controller hose = {
Chakra Divia1fef712017-06-05 23:09:30 +053080config_table: pci_pip405_config_table,
81fixup_irq : pci_pip405_fixup_irq,
wdenkc6097192002-11-03 00:24:07 +000082};
83
wdenkb02744a2003-04-05 00:53:31 +000084
stroesef5dd4102003-02-14 11:21:23 +000085void pci_init_board(void)
wdenkc6097192002-11-03 00:24:07 +000086{
87 /*we want the ptrs to RAM not flash (ie don't use init list)*/
88 hose.fixup_irq = pci_pip405_fixup_irq;
89 hose.config_table = pci_pip405_config_table;
wdenkb02744a2003-04-05 00:53:31 +000090#ifdef DEBUG
Chakra Divia1fef712017-06-05 23:09:30 +053091 printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",
92 pci_pip405_fixup_irq, pci_pip405_config_table, hose);
wdenkb02744a2003-04-05 00:53:31 +000093#endif
wdenkc6097192002-11-03 00:24:07 +000094 pci_405gp_init(&hose);
95}
96
97#endif /* CONFIG_PCI */
98#endif /* CONFIG_405GP */