Wolfgang Denk | 52744b4 | 2013-07-28 22:12:45 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | 815c967 | 2013-09-17 11:24:06 +0200 | [diff] [blame] | 2 | * SPDX-License-Identifier: GPL-2.0 IBM-pibs |
Wolfgang Denk | 52744b4 | 2013-07-28 22:12:45 +0200 | [diff] [blame] | 3 | */ |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 4 | |
| 5 | #ifndef __PPC4XX_H__ |
| 6 | #define __PPC4XX_H__ |
| 7 | |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 8 | /* |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 9 | * Include SoC specific headers |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 10 | */ |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 11 | #if defined(CONFIG_405EP) |
| 12 | #include <asm/ppc405ep.h> |
| 13 | #endif |
| 14 | |
| 15 | #if defined(CONFIG_405EX) |
| 16 | #include <asm/ppc405ex.h> |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 17 | #endif |
| 18 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 19 | #if defined(CONFIG_405EZ) |
| 20 | #include <asm/ppc405ez.h> |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 21 | #endif |
| 22 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 23 | #if defined(CONFIG_405GP) |
| 24 | #include <asm/ppc405gp.h> |
| 25 | #endif |
| 26 | |
| 27 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
| 28 | #include <asm/ppc440ep_gr.h> |
| 29 | #endif |
| 30 | |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 31 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 32 | #include <asm/ppc440epx_grx.h> |
| 33 | #endif |
| 34 | |
| 35 | #if defined(CONFIG_440GP) |
| 36 | #include <asm/ppc440gp.h> |
| 37 | #endif |
| 38 | |
| 39 | #if defined(CONFIG_440GX) |
| 40 | #include <asm/ppc440gx.h> |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 41 | #endif |
| 42 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 43 | #if defined(CONFIG_440SP) |
| 44 | #include <asm/ppc440sp.h> |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 45 | #endif |
| 46 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 47 | #if defined(CONFIG_440SPE) |
| 48 | #include <asm/ppc440spe.h> |
Stefan Roese | 982511e | 2009-05-20 10:58:01 +0200 | [diff] [blame] | 49 | #endif |
| 50 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 51 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 52 | #include <asm/ppc460ex_gt.h> |
| 53 | #endif |
Prodyut Hazarika | 038f0d8 | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 54 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 55 | #if defined(CONFIG_460SX) |
| 56 | #include <asm/ppc460sx.h> |
| 57 | #endif |
Prodyut Hazarika | 038f0d8 | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 58 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 59 | /* |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 60 | * Common registers for all SoC's |
| 61 | */ |
| 62 | /* DCR registers */ |
| 63 | #define PLB3A0_ACR 0x0077 |
| 64 | #define PLB4A0_ACR 0x0081 |
| 65 | #define PLB4A1_ACR 0x0089 |
Prodyut Hazarika | 038f0d8 | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 66 | |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 67 | /* CPR register declarations */ |
| 68 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 69 | #define PLB4Ax_ACR_PPM_MASK 0xf0000000 |
| 70 | #define PLB4Ax_ACR_PPM_FIXED 0x00000000 |
| 71 | #define PLB4Ax_ACR_PPM_FAIR 0xd0000000 |
| 72 | #define PLB4Ax_ACR_HBU_MASK 0x08000000 |
| 73 | #define PLB4Ax_ACR_HBU_DISABLED 0x00000000 |
| 74 | #define PLB4Ax_ACR_HBU_ENABLED 0x08000000 |
| 75 | #define PLB4Ax_ACR_RDP_MASK 0x06000000 |
| 76 | #define PLB4Ax_ACR_RDP_DISABLED 0x00000000 |
| 77 | #define PLB4Ax_ACR_RDP_2DEEP 0x02000000 |
| 78 | #define PLB4Ax_ACR_RDP_3DEEP 0x04000000 |
| 79 | #define PLB4Ax_ACR_RDP_4DEEP 0x06000000 |
| 80 | #define PLB4Ax_ACR_WRP_MASK 0x01000000 |
| 81 | #define PLB4Ax_ACR_WRP_DISABLED 0x00000000 |
| 82 | #define PLB4Ax_ACR_WRP_2DEEP 0x01000000 |
Prodyut Hazarika | 038f0d8 | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 83 | |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 84 | /* |
| 85 | * External Bus Controller |
| 86 | */ |
| 87 | /* Values for EBC0_CFGADDR register - indirect addressing of these regs */ |
| 88 | #define PB0CR 0x00 /* periph bank 0 config reg */ |
| 89 | #define PB1CR 0x01 /* periph bank 1 config reg */ |
| 90 | #define PB2CR 0x02 /* periph bank 2 config reg */ |
| 91 | #define PB3CR 0x03 /* periph bank 3 config reg */ |
| 92 | #define PB4CR 0x04 /* periph bank 4 config reg */ |
| 93 | #define PB5CR 0x05 /* periph bank 5 config reg */ |
| 94 | #define PB6CR 0x06 /* periph bank 6 config reg */ |
| 95 | #define PB7CR 0x07 /* periph bank 7 config reg */ |
| 96 | #define PB0AP 0x10 /* periph bank 0 access parameters */ |
| 97 | #define PB1AP 0x11 /* periph bank 1 access parameters */ |
| 98 | #define PB2AP 0x12 /* periph bank 2 access parameters */ |
| 99 | #define PB3AP 0x13 /* periph bank 3 access parameters */ |
| 100 | #define PB4AP 0x14 /* periph bank 4 access parameters */ |
| 101 | #define PB5AP 0x15 /* periph bank 5 access parameters */ |
| 102 | #define PB6AP 0x16 /* periph bank 6 access parameters */ |
| 103 | #define PB7AP 0x17 /* periph bank 7 access parameters */ |
| 104 | #define PBEAR 0x20 /* periph bus error addr reg */ |
| 105 | #define PBESR0 0x21 /* periph bus error status reg 0 */ |
| 106 | #define PBESR1 0x22 /* periph bus error status reg 1 */ |
| 107 | #define EBC0_CFG 0x23 /* external bus configuration reg */ |
| 108 | |
| 109 | /* |
| 110 | * GPIO macro register defines |
| 111 | */ |
| 112 | /* todo: merge with gpio.h header */ |
| 113 | #define GPIO_BASE GPIO0_BASE |
| 114 | |
| 115 | #define GPIO0_OR (GPIO0_BASE + 0x0) |
| 116 | #define GPIO0_TCR (GPIO0_BASE + 0x4) |
| 117 | #define GPIO0_OSRL (GPIO0_BASE + 0x8) |
| 118 | #define GPIO0_OSRH (GPIO0_BASE + 0xC) |
| 119 | #define GPIO0_TSRL (GPIO0_BASE + 0x10) |
| 120 | #define GPIO0_TSRH (GPIO0_BASE + 0x14) |
| 121 | #define GPIO0_ODR (GPIO0_BASE + 0x18) |
| 122 | #define GPIO0_IR (GPIO0_BASE + 0x1C) |
| 123 | #define GPIO0_RR1 (GPIO0_BASE + 0x20) |
| 124 | #define GPIO0_RR2 (GPIO0_BASE + 0x24) |
| 125 | #define GPIO0_RR3 (GPIO0_BASE + 0x28) |
| 126 | #define GPIO0_ISR1L (GPIO0_BASE + 0x30) |
| 127 | #define GPIO0_ISR1H (GPIO0_BASE + 0x34) |
| 128 | #define GPIO0_ISR2L (GPIO0_BASE + 0x38) |
| 129 | #define GPIO0_ISR2H (GPIO0_BASE + 0x3C) |
| 130 | #define GPIO0_ISR3L (GPIO0_BASE + 0x40) |
| 131 | #define GPIO0_ISR3H (GPIO0_BASE + 0x44) |
| 132 | |
| 133 | #define GPIO1_OR (GPIO1_BASE + 0x0) |
| 134 | #define GPIO1_TCR (GPIO1_BASE + 0x4) |
| 135 | #define GPIO1_OSRL (GPIO1_BASE + 0x8) |
| 136 | #define GPIO1_OSRH (GPIO1_BASE + 0xC) |
| 137 | #define GPIO1_TSRL (GPIO1_BASE + 0x10) |
| 138 | #define GPIO1_TSRH (GPIO1_BASE + 0x14) |
| 139 | #define GPIO1_ODR (GPIO1_BASE + 0x18) |
| 140 | #define GPIO1_IR (GPIO1_BASE + 0x1C) |
| 141 | #define GPIO1_RR1 (GPIO1_BASE + 0x20) |
| 142 | #define GPIO1_RR2 (GPIO1_BASE + 0x24) |
| 143 | #define GPIO1_RR3 (GPIO1_BASE + 0x28) |
| 144 | #define GPIO1_ISR1L (GPIO1_BASE + 0x30) |
| 145 | #define GPIO1_ISR1H (GPIO1_BASE + 0x34) |
| 146 | #define GPIO1_ISR2L (GPIO1_BASE + 0x38) |
| 147 | #define GPIO1_ISR2H (GPIO1_BASE + 0x3C) |
| 148 | #define GPIO1_ISR3L (GPIO1_BASE + 0x40) |
| 149 | #define GPIO1_ISR3H (GPIO1_BASE + 0x44) |
| 150 | |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 151 | /* General Purpose Timer (GPT) Register Offsets */ |
| 152 | #define GPT0_TBC 0x00000000 |
| 153 | #define GPT0_IM 0x00000018 |
| 154 | #define GPT0_ISS 0x0000001C |
| 155 | #define GPT0_ISC 0x00000020 |
| 156 | #define GPT0_IE 0x00000024 |
| 157 | #define GPT0_COMP0 0x00000080 |
| 158 | #define GPT0_COMP1 0x00000084 |
| 159 | #define GPT0_COMP2 0x00000088 |
| 160 | #define GPT0_COMP3 0x0000008C |
| 161 | #define GPT0_COMP4 0x00000090 |
| 162 | #define GPT0_COMP5 0x00000094 |
| 163 | #define GPT0_COMP6 0x00000098 |
| 164 | #define GPT0_MASK0 0x000000C0 |
| 165 | #define GPT0_MASK1 0x000000C4 |
| 166 | #define GPT0_MASK2 0x000000C8 |
| 167 | #define GPT0_MASK3 0x000000CC |
| 168 | #define GPT0_MASK4 0x000000D0 |
| 169 | #define GPT0_MASK5 0x000000D4 |
| 170 | #define GPT0_MASK6 0x000000D8 |
| 171 | #define GPT0_DCT0 0x00000110 |
| 172 | #define GPT0_DCIS 0x0000011C |
Prodyut Hazarika | 038f0d8 | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 173 | |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 174 | #if defined(CONFIG_440) |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 175 | #include <asm/ppc440.h> |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 176 | #else |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 177 | #include <asm/ppc405.h> |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 178 | #endif |
| 179 | |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 180 | #include <asm/ppc4xx-sdram.h> |
Stefan Roese | c415db6 | 2008-06-24 17:18:50 +0200 | [diff] [blame] | 181 | #include <asm/ppc4xx-ebc.h> |
Ricardo Ribalda Delgado | 95c5020 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 182 | #if !defined(CONFIG_XILINX_440) |
Stefan Roese | 41b1746 | 2008-06-25 10:59:22 +0200 | [diff] [blame] | 183 | #include <asm/ppc4xx-uic.h> |
Ricardo Ribalda Delgado | 95c5020 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 184 | #endif |
Stefan Roese | 39271dd | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 185 | |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 186 | /* |
Grant Erickson | b693341 | 2008-05-22 14:44:14 -0700 | [diff] [blame] | 187 | * Macro for generating register field mnemonics |
| 188 | */ |
| 189 | #define PPC_REG_BITS 32 |
| 190 | #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) |
| 191 | |
| 192 | /* |
| 193 | * Elide casts when assembling register mnemonics |
| 194 | */ |
| 195 | #ifndef __ASSEMBLY__ |
| 196 | #define static_cast(type, val) (type)(val) |
| 197 | #else |
| 198 | #define static_cast(type, val) (val) |
| 199 | #endif |
| 200 | |
| 201 | /* |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 202 | * Common stuff for 4xx (405 and 440) |
| 203 | */ |
| 204 | |
Niklaus Giger | 3c8ef44 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 205 | #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 206 | #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) |
| 207 | |
| 208 | #define RESET_VECTOR 0xfffffffc |
Niklaus Giger | 3c8ef44 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 209 | #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for |
| 210 | cache line aligned data. */ |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 211 | |
| 212 | #define CPR0_DCR_BASE 0x0C |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 213 | #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) |
| 214 | #define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 215 | |
| 216 | #define SDR_DCR_BASE 0x0E |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 217 | #define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) |
| 218 | #define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 219 | |
| 220 | #define SDRAM_DCR_BASE 0x10 |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 221 | #define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) |
| 222 | #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 223 | |
| 224 | #define EBC_DCR_BASE 0x12 |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 225 | #define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) |
| 226 | #define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 227 | |
| 228 | /* |
| 229 | * Macros for indirect DCR access |
| 230 | */ |
Niklaus Giger | 3c8ef44 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 231 | #define mtcpr(reg, d) \ |
| 232 | do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0) |
| 233 | #define mfcpr(reg, d) \ |
| 234 | do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0) |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 235 | |
Niklaus Giger | 3c8ef44 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 236 | #define mtebc(reg, d) \ |
| 237 | do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0) |
| 238 | #define mfebc(reg, d) \ |
| 239 | do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0) |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 240 | |
Niklaus Giger | 3c8ef44 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 241 | #define mtsdram(reg, d) \ |
| 242 | do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0) |
| 243 | #define mfsdram(reg, d) \ |
| 244 | do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0) |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 245 | |
Niklaus Giger | 3c8ef44 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 246 | #define mtsdr(reg, d) \ |
| 247 | do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0) |
| 248 | #define mfsdr(reg, d) \ |
| 249 | do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0) |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 250 | |
| 251 | #ifndef __ASSEMBLY__ |
| 252 | |
| 253 | typedef struct |
| 254 | { |
| 255 | unsigned long freqDDR; |
| 256 | unsigned long freqEBC; |
| 257 | unsigned long freqOPB; |
| 258 | unsigned long freqPCI; |
| 259 | unsigned long freqPLB; |
| 260 | unsigned long freqTmrClk; |
| 261 | unsigned long freqUART; |
| 262 | unsigned long freqProcessor; |
| 263 | unsigned long freqVCOHz; |
| 264 | unsigned long freqVCOMhz; /* in MHz */ |
| 265 | unsigned long pciClkSync; /* PCI clock is synchronous */ |
| 266 | unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ |
| 267 | unsigned long pllExtBusDiv; |
| 268 | unsigned long pllFbkDiv; |
| 269 | unsigned long pllFwdDiv; |
| 270 | unsigned long pllFwdDivA; |
| 271 | unsigned long pllFwdDivB; |
| 272 | unsigned long pllOpbDiv; |
| 273 | unsigned long pllPciDiv; |
| 274 | unsigned long pllPlbDiv; |
| 275 | } PPC4xx_SYS_INFO; |
| 276 | |
Adam Graham | 97a5581 | 2008-09-03 12:26:59 -0700 | [diff] [blame] | 277 | static inline u32 get_mcsr(void) |
| 278 | { |
| 279 | u32 val; |
| 280 | |
| 281 | asm volatile("mfspr %0, 0x23c" : "=r" (val) :); |
| 282 | return val; |
| 283 | } |
| 284 | |
| 285 | static inline void set_mcsr(u32 val) |
| 286 | { |
| 287 | asm volatile("mtspr 0x23c, %0" : "=r" (val) :); |
| 288 | } |
| 289 | |
Stefan Roese | cd47b18 | 2009-10-19 14:06:23 +0200 | [diff] [blame] | 290 | int ppc4xx_pci_sync_clock_config(u32 async); |
| 291 | |
Simon Glass | abd7d92 | 2017-05-17 08:22:39 -0600 | [diff] [blame] | 292 | unsigned long get_OPB_freq(void); |
| 293 | unsigned long get_PCI_freq(void); |
| 294 | |
Simon Glass | 50e9770 | 2017-05-17 08:23:04 -0600 | [diff] [blame] | 295 | typedef PPC4xx_SYS_INFO sys_info_t; |
| 296 | int ppc440spe_revB(void); |
| 297 | void get_sys_info(sys_info_t *); |
| 298 | |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 299 | #endif /* __ASSEMBLY__ */ |
| 300 | |
Adam Graham | c31ff68 | 2008-10-08 10:13:19 -0700 | [diff] [blame] | 301 | /* for multi-cpu support */ |
| 302 | #define NA_OR_UNKNOWN_CPU -1 |
| 303 | |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 304 | #endif /* __PPC4XX_H__ */ |