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git01.mediatek.com / filogic / uboot / 6c8ecef158865f4b5fdd7450aa03c7ffa92d1e47 / . / configs / nanopi-r5c-rk3568_defconfig
blob: badac5805ddb24d53702213df5f9399f803754fc [file] [log] [blame]
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT=y
3CONFIG_COUNTER_FREQUENCY=24000000
4CONFIG_ARCH_ROCKCHIP=y
5CONFIG_TEXT_BASE=0x00a00000
6CONFIG_SPL_LIBCOMMON_SUPPORT=y
7CONFIG_SPL_LIBGENERIC_SUPPORT=y
8CONFIG_NR_DRAM_BANKS=2
9CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
10CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
11CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
12CONFIG_ROCKCHIP_RK3568=y
13CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
14CONFIG_SPL_SERIAL=y
15CONFIG_SPL_STACK_R_ADDR=0x600000
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]16CONFIG_SPL_STACK=0x400000
17CONFIG_DEBUG_UART_BASE=0xFE660000
18CONFIG_DEBUG_UART_CLOCK=24000000
19CONFIG_SYS_LOAD_ADDR=0xc00800
20CONFIG_DEBUG_UART=y
21CONFIG_FIT=y
22CONFIG_FIT_VERBOSE=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame^]23CONFIG_SPL_FIT_SIGNATURE=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]24CONFIG_SPL_LOAD_FIT=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame^]25CONFIG_LEGACY_IMAGE_FORMAT=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]26CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
27# CONFIG_DISPLAY_CPUINFO is not set
28CONFIG_DISPLAY_BOARDINFO_LATE=y
29CONFIG_SPL_MAX_SIZE=0x40000
30CONFIG_SPL_PAD_TO=0x7f8000
31CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
32CONFIG_SPL_BSS_START_ADDR=0x4000000
33CONFIG_SPL_BSS_MAX_SIZE=0x4000
34# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
35# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
36CONFIG_SPL_STACK_R=y
37CONFIG_SPL_ATF=y
38CONFIG_CMD_GPIO=y
39CONFIG_CMD_GPT=y
40CONFIG_CMD_I2C=y
41CONFIG_CMD_MMC=y
42CONFIG_CMD_USB=y
43CONFIG_CMD_PMIC=y
44CONFIG_CMD_REGULATOR=y
45# CONFIG_SPL_DOS_PARTITION is not set
46CONFIG_SPL_OF_CONTROL=y
47CONFIG_OF_LIVE=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame^]48CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]49CONFIG_SPL_DM_WARN=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame^]50CONFIG_SPL_DM_SEQ_ALIAS=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]51CONFIG_SPL_REGMAP=y
52CONFIG_SPL_SYSCON=y
53CONFIG_SPL_CLK=y
54CONFIG_ROCKCHIP_GPIO=y
55CONFIG_SYS_I2C_ROCKCHIP=y
56CONFIG_MISC=y
57CONFIG_SUPPORT_EMMC_RPMB=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame^]58CONFIG_MMC_HS200_SUPPORT=y
59CONFIG_SPL_MMC_HS200_SUPPORT=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]60CONFIG_MMC_DW=y
61CONFIG_MMC_DW_ROCKCHIP=y
62CONFIG_MMC_SDHCI=y
63CONFIG_MMC_SDHCI_SDMA=y
64CONFIG_MMC_SDHCI_ROCKCHIP=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]65CONFIG_PHY_ROCKCHIP_INNO_USB2=y
66CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame^]67CONFIG_SPL_PINCTRL=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]68CONFIG_DM_PMIC=y
69CONFIG_PMIC_RK8XX=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]70CONFIG_REGULATOR_RK8XX=y
71CONFIG_PWM_ROCKCHIP=y
72CONFIG_SPL_RAM=y
73CONFIG_BAUDRATE=1500000
74CONFIG_DEBUG_UART_SHIFT=2
75CONFIG_SYS_NS16550_MEM32=y
76CONFIG_SYSRESET=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]77CONFIG_USB=y
78CONFIG_USB_XHCI_HCD=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]79CONFIG_USB_EHCI_HCD=y
80CONFIG_USB_EHCI_GENERIC=y
81CONFIG_USB_OHCI_HCD=y
82CONFIG_USB_OHCI_GENERIC=y
83CONFIG_USB_DWC3=y
Jonas Karlmand0de5dc2023-07-30 22:59:59 +0000[diff] [blame]84CONFIG_USB_DWC3_GENERIC=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]85CONFIG_ERRNO_STR=y