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git01.mediatek.com / filogic / uboot / 6c7727723a4e930a5aa9c6e898f650774d66337a / . / arch / arm / mach-k3 / arm64-mmu.c
blob: 7f908eee803b685b5c984069fb7ce313c1cfdd5d [file] [log] [blame]
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * K3: ARM64 MMU setup
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
Michal Simek7f60b232019-01-17 08:22:43 +0100[diff] [blame]7 * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]8 *
9 */
10
11#include <common.h>
12#include <asm/system.h>
13#include <asm/armv8/mmu.h>
14
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]15#ifdef CONFIG_SOC_K3_AM6
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]16/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
Suman Annaf359afb2019-09-04 16:01:49 +0530[diff] [blame]17#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]18
19/* ToDo: Add 64bit IO */
20struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
21 {
22 .virt = 0x0UL,
23 .phys = 0x0UL,
24 .size = 0x80000000UL,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
26 PTE_BLOCK_NON_SHARE |
27 PTE_BLOCK_PXN | PTE_BLOCK_UXN
28 }, {
29 .virt = 0x80000000UL,
30 .phys = 0x80000000UL,
Suman Annaf359afb2019-09-04 16:01:49 +0530[diff] [blame]31 .size = 0x20000000UL,
32 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
33 PTE_BLOCK_INNER_SHARE
34 }, {
35 .virt = 0xa0000000UL,
36 .phys = 0xa0000000UL,
37 .size = 0x02100000UL,
38 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
39 PTE_BLOCK_INNER_SHARE
40 }, {
41 .virt = 0xa2100000UL,
42 .phys = 0xa2100000UL,
43 .size = 0x5df00000UL,
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]44 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45 PTE_BLOCK_INNER_SHARE
46 }, {
47 .virt = 0x880000000UL,
48 .phys = 0x880000000UL,
49 .size = 0x80000000UL,
50 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
51 PTE_BLOCK_INNER_SHARE
52 }, {
53 /* List terminator */
54 0,
55 }
56};
57
58struct mm_region *mem_map = am654_mem_map;
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]59#endif /* CONFIG_SOC_K3_AM6 */
60
61#ifdef CONFIG_SOC_K3_J721E
62/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
63#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
64
65/* ToDo: Add 64bit IO */
66struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
67 {
68 .virt = 0x0UL,
69 .phys = 0x0UL,
70 .size = 0x80000000UL,
71 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
72 PTE_BLOCK_NON_SHARE |
73 PTE_BLOCK_PXN | PTE_BLOCK_UXN
74 }, {
75 .virt = 0x80000000UL,
76 .phys = 0x80000000UL,
77 .size = 0x20000000UL,
78 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
79 PTE_BLOCK_INNER_SHARE
80 }, {
81 .virt = 0xa0000000UL,
82 .phys = 0xa0000000UL,
Kedar Chitnis0e01e3e2019-09-04 16:01:50 +0530[diff] [blame]83 .size = 0x1bc00000UL,
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]84 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
85 PTE_BLOCK_NON_SHARE
86 }, {
Kedar Chitnis0e01e3e2019-09-04 16:01:50 +0530[diff] [blame]87 .virt = 0xbbc00000UL,
88 .phys = 0xbbc00000UL,
89 .size = 0x44400000UL,
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]90 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
91 PTE_BLOCK_INNER_SHARE
92 }, {
93 .virt = 0x880000000UL,
94 .phys = 0x880000000UL,
95 .size = 0x80000000UL,
96 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
97 PTE_BLOCK_INNER_SHARE
98 }, {
99 .virt = 0x500000000UL,
100 .phys = 0x500000000UL,
101 .size = 0x400000000UL,
102 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
103 PTE_BLOCK_NON_SHARE |
104 PTE_BLOCK_PXN | PTE_BLOCK_UXN
105 }, {
106 /* List terminator */
107 0,
108 }
109};
110
111struct mm_region *mem_map = j721e_mem_map;
112#endif /* CONFIG_SOC_K3_J721E */