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git01.mediatek.com / filogic / uboot / 6c55d0d3cc82e354a32ee4a59135edabf5afcb1d / . / drivers / clk / sunxi / clk_h6.c
blob: 041bc5e80ed3f67d85d6ef359de6423e4e316d7c [file] [log] [blame]
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]12#include <dt-bindings/clock/sun50i-h6-ccu.h>
13#include <dt-bindings/reset/sun50i-h6-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]15
16static struct ccu_clk_gate h6_gates[] = {
Andre Przywara3e9aa0b2022-05-04 22:10:28 +0100[diff] [blame]17 [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
18
Andre Przywara2d1864f2022-05-05 01:25:43 +0100[diff] [blame]19 [CLK_APB1] = GATE_DUMMY,
20
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]21 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
22 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
23 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]24 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
25 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
26 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
27 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]28
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]29 [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
30 [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
31 [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
32 [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
33
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]34 [CLK_SPI0] = GATE(0x940, BIT(31)),
35 [CLK_SPI1] = GATE(0x944, BIT(31)),
36
37 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
38 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]39
40 [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
Andre Przywara60e6efd2019-06-23 15:09:48 +0100[diff] [blame]41
42 [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
43 [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
44
45 [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
46
47 [CLK_USB_HSIC] = GATE(0xa7c, BIT(26)),
48 [CLK_USB_HSIC_12M] = GATE(0xa7c, BIT(27)),
49 [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
50 [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
51
52 [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
53 [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
54 [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
Samuel Hollandd73b8a52021-02-07 23:57:20 -0600[diff] [blame]55 [CLK_BUS_XHCI] = GATE(0xa8c, BIT(5)),
Andre Przywara60e6efd2019-06-23 15:09:48 +0100[diff] [blame]56 [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
57 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]58};
59
60static struct ccu_reset h6_resets[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]61 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
62 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
63 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]64 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
65 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
66 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
67 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]68
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]69 [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
70 [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
71 [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
72 [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
73
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]74 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
75 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]76
77 [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
Andre Przywara60e6efd2019-06-23 15:09:48 +0100[diff] [blame]78
79 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
80
81 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
82
83 [RST_USB_HSIC] = RESET(0xa7c, BIT(28)),
84 [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
85
86 [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
87 [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
88 [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
Samuel Hollandd73b8a52021-02-07 23:57:20 -0600[diff] [blame]89 [RST_BUS_XHCI] = RESET(0xa8c, BIT(21)),
Andre Przywara60e6efd2019-06-23 15:09:48 +0100[diff] [blame]90 [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
91 [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]92};
93
Samuel Holland751c6c62022-05-09 00:29:34 -0500[diff] [blame]94const struct ccu_desc h6_ccu_desc = {
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]95 .gates = h6_gates,
96 .resets = h6_resets,
Samuel Holland84436502022-05-09 00:29:31 -0500[diff] [blame]97 .num_gates = ARRAY_SIZE(h6_gates),
98 .num_resets = ARRAY_SIZE(h6_resets),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]99};