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git01.mediatek.com / filogic / uboot / 6c55d0d3cc82e354a32ee4a59135edabf5afcb1d / . / configs / cobra5272_defconfig
blob: e8301c6301a54d10d42496682b7e47dda9716e8b [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1CONFIG_M68K=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0xFFE00000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]3CONFIG_SYS_MALLOC_LEN=0x40000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]4CONFIG_ENV_SIZE=0x2000
5CONFIG_ENV_SECT_SIZE=0x2000
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]6CONFIG_DEFAULT_DEVICE_TREE="cobra5272"
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]7CONFIG_SYS_LOAD_ADDR=0x20000
8CONFIG_ENV_ADDR=0xFFE04000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_TARGET_COBRA5272=y
Tom Rini06eb4542022-03-23 17:19:49 -0400[diff] [blame]10CONFIG_MCFTMR=y
Tom Rini03becca2022-03-24 17:18:05 -0400[diff] [blame]11CONFIG_SYS_MONITOR_BASE=0xFFE00400
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]12CONFIG_BOOTDELAY=5
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]13# CONFIG_DISPLAY_BOARDINFO is not set
Tom Rini47805502022-05-12 16:45:08 -0400[diff] [blame]14CONFIG_SYS_MALLOC_BOOTPARAMS=y
Adam Ford58dbf862018-02-06 07:58:59 -0600[diff] [blame]15# CONFIG_CMDLINE_EDITING is not set
16# CONFIG_AUTO_COMPLETE is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]17CONFIG_SYS_PROMPT="COBRA > "
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]18CONFIG_SYS_PBSIZE=281
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]19CONFIG_CMD_IMLS=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]20# CONFIG_CMD_LOADB is not set
21# CONFIG_CMD_LOADS is not set
22# CONFIG_CMD_SETEXPR is not set
Tom Rini1c47c4a2022-02-25 11:19:50 -0500[diff] [blame]23CONFIG_BOOTP_BOOTFILESIZE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]24CONFIG_CMD_PING=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]25CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rini97b04182022-03-18 08:38:21 -0400[diff] [blame]26CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
Tom Rinif9d5e832022-03-18 08:38:25 -0400[diff] [blame]27CONFIG_SYS_RX_ETH_BUFFER=8
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]28CONFIG_SYS_BR0_PRELIM_BOOL=y
29CONFIG_SYS_BR0_PRELIM=0xFFE00201
30CONFIG_SYS_OR0_PRELIM=0xFFE00014
31CONFIG_SYS_BR1_PRELIM_BOOL=y
32CONFIG_SYS_BR1_PRELIM=0x0
33CONFIG_SYS_OR1_PRELIM=0x0
34CONFIG_SYS_BR2_PRELIM_BOOL=y
35CONFIG_SYS_BR2_PRELIM=0x0
36CONFIG_SYS_OR2_PRELIM=0x0
37CONFIG_SYS_BR3_PRELIM_BOOL=y
38CONFIG_SYS_BR3_PRELIM=0x0
39CONFIG_SYS_OR3_PRELIM=0x0
40CONFIG_SYS_BR4_PRELIM_BOOL=y
41CONFIG_SYS_BR4_PRELIM=0x0
42CONFIG_SYS_OR4_PRELIM=0x0
43CONFIG_SYS_BR5_PRELIM_BOOL=y
44CONFIG_SYS_BR5_PRELIM=0x0
45CONFIG_SYS_OR5_PRELIM=0x0
46CONFIG_SYS_BR6_PRELIM_BOOL=y
47CONFIG_SYS_BR6_PRELIM=0x0
48CONFIG_SYS_OR6_PRELIM=0x0
49CONFIG_SYS_BR7_PRELIM_BOOL=y
50CONFIG_SYS_BR7_PRELIM=0x701
51CONFIG_SYS_OR7_PRELIM=0xFF00007C
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]52CONFIG_MTD_NOR_FLASH=y
Tom Rinid38112c2022-07-23 13:05:04 -0400[diff] [blame]53CONFIG_SYS_MAX_FLASH_SECT=11
Patrick Delaunay1576abf2022-01-04 14:24:00 +0100[diff] [blame]54CONFIG_USE_SYS_MAX_FLASH_BANKS=y
Angelo Durgehello6e366ca2019-11-15 23:54:14 +0100[diff] [blame]55CONFIG_DM_ETH=y
56CONFIG_MCFFEC=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]57CONFIG_MII=y
Philipp Tomsich29c8bc02017-03-17 20:34:53 +0100[diff] [blame]58CONFIG_BAUDRATE=19200
Tom Riniae6fd8e2021-10-30 23:03:53 -0400[diff] [blame]59CONFIG_MCFUART=y