blob: 40ccd16587495d88a582b50f23b3b381fa2eab95 [file] [log] [blame]
Stefan Herbrechtsmeier10ff2882022-08-05 08:16:28 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017-2022 Weidmüller Interface GmbH & Co. KG
4 * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
5 *
6 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved.
8 *
9 * (C) Copyright 2008
10 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
11 *
12 * (C) Copyright 2004
13 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
14 *
15 * (C) Copyright 2002-2004
16 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
17 *
18 * (C) Copyright 2003
19 * Texas Instruments <www.ti.com>
20 *
21 * (C) Copyright 2002
22 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
23 * Marius Groeger <mgroeger@sysgo.de>
24 *
25 * (C) Copyright 2002
26 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
27 * Alex Zuepke <azu@sysgo.de>
28 */
29
30#include <common.h>
31#include <dm.h>
32#include <fdtdec.h>
33#include <timer.h>
34#include <linux/bitops.h>
35
36#include <asm/io.h>
37
38#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
39#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */
40#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */
41
42#define TIMER_LOAD_VAL 0xFFFFFFFF
43
44struct arm_twd_timer_regs {
45 u32 load; /* Timer Load Register */
46 u32 counter; /* Timer Counter Register */
47 u32 control; /* Timer Control Register */
48};
49
50struct arm_twd_timer_priv {
51 struct arm_twd_timer_regs *base;
52};
53
54static u64 arm_twd_timer_get_count(struct udevice *dev)
55{
56 struct arm_twd_timer_priv *priv = dev_get_priv(dev);
57 struct arm_twd_timer_regs *regs = priv->base;
58 u32 count = TIMER_LOAD_VAL - readl(&regs->counter);
59
60 return timer_conv_64(count);
61}
62
63static int arm_twd_timer_probe(struct udevice *dev)
64{
65 struct arm_twd_timer_priv *priv = dev_get_priv(dev);
66 struct arm_twd_timer_regs *regs;
67 fdt_addr_t addr;
68
69 addr = dev_read_addr(dev);
70 if (addr == FDT_ADDR_T_NONE)
71 return -EINVAL;
72
73 priv->base = (struct arm_twd_timer_regs *)addr;
74
75 regs = priv->base;
76
77 /* Load the timer counter register */
78 writel(0xFFFFFFFF, &regs->load);
79
80 /*
81 * Start the A9Timer device
82 * Enable Auto reload mode, Clear prescaler control bits
83 * Set prescaler value, Enable the decrementer
84 */
85 clrsetbits_le32(&regs->control, SCUTIMER_CONTROL_PRESCALER_MASK,
86 SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
87 SCUTIMER_CONTROL_ENABLE_MASK);
88
89 return 0;
90}
91
92static const struct timer_ops arm_twd_timer_ops = {
93 .get_count = arm_twd_timer_get_count,
94};
95
96static const struct udevice_id arm_twd_timer_ids[] = {
97 { .compatible = "arm,cortex-a9-twd-timer" },
98 {}
99};
100
101U_BOOT_DRIVER(arm_twd_timer) = {
102 .name = "arm_twd_timer",
103 .id = UCLASS_TIMER,
104 .of_match = arm_twd_timer_ids,
105 .priv_auto = sizeof(struct arm_twd_timer_priv),
106 .probe = arm_twd_timer_probe,
107 .ops = &arm_twd_timer_ops,
108};