Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 6bf9755c89c4b008b47f666478441520dab0ffcb / . / arch / arm / mach-k3 / j7200 / clk-data.c
blob: 93c067079ab6e9148e530c2a11334b52720d50e3 [file] [log] [blame]
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * J7200 specific clock platform data
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
6 */
7#include "k3-clk.h"
8
9static const char * const gluelogic_hfosc0_clkout_parents[] = {
10 "osc_19_2_mhz",
11 "osc_20_mhz",
12 "osc_24_mhz",
13 "osc_25_mhz",
14 "osc_26_mhz",
15 "osc_27_mhz",
16};
17
18static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
19 "board_0_mcu_ospi0_dqs_out",
20 "fss_mcu_0_ospi_0_ospi_oclk_clk",
21};
22
23static const char * const wkup_fref_clksel_out0_parents[] = {
24 "gluelogic_hfosc0_clkout",
25 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
26};
27
28static const char * const main_pll_hfosc_sel_out1_parents[] = {
29 "gluelogic_hfosc0_clkout",
30 "board_0_hfosc1_clk_out",
31};
32
33static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
34 "wkup_fref_clksel_out0",
35 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
36};
37
38static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
39 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
40 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
41};
42
43static const char * const mcuusart_clk_sel_out0_parents[] = {
44 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
45 "postdiv2_16fft_main_1_hsdivout5_clk",
46};
47
48static const char * const wkup_gpio0_clksel_out0_parents[] = {
49 "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
50 "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
51 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
52 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
53};
54
55static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
56 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
57 "gluelogic_hfosc0_clkout",
58};
59
60static const char * const main_pll_hfosc_sel_out0_parents[] = {
61 "gluelogic_hfosc0_clkout",
62 "board_0_hfosc1_clk_out",
63};
64
65static const char * const main_pll_hfosc_sel_out12_parents[] = {
66 "gluelogic_hfosc0_clkout",
67 "board_0_hfosc1_clk_out",
68};
69
70static const char * const main_pll_hfosc_sel_out14_parents[] = {
71 "gluelogic_hfosc0_clkout",
72 "board_0_hfosc1_clk_out",
73};
74
75static const char * const main_pll_hfosc_sel_out2_parents[] = {
76 "gluelogic_hfosc0_clkout",
77 "board_0_hfosc1_clk_out",
78};
79
80static const char * const main_pll_hfosc_sel_out3_parents[] = {
81 "gluelogic_hfosc0_clkout",
82 "board_0_hfosc1_clk_out",
83};
84
85static const char * const main_pll_hfosc_sel_out4_parents[] = {
86 "gluelogic_hfosc0_clkout",
87 "board_0_hfosc1_clk_out",
88};
89
90static const char * const main_pll_hfosc_sel_out7_parents[] = {
91 "gluelogic_hfosc0_clkout",
92 "board_0_hfosc1_clk_out",
93};
94
95static const char * const main_pll_hfosc_sel_out8_parents[] = {
96 "gluelogic_hfosc0_clkout",
97 "board_0_hfosc1_clk_out",
98};
99
100static const char * const usb0_refclk_sel_out0_parents[] = {
101 "gluelogic_hfosc0_clkout",
102 "board_0_hfosc1_clk_out",
103};
104
105static const char * const wkup_obsclk_mux_out0_parents[] = {
106 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
107 NULL,
108 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
109 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
110 "hsdiv4_16fft_mcu_1_hsdivout1_clk",
111 "hsdiv4_16fft_mcu_1_hsdivout2_clk",
112 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
113 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
114 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
115 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
116 "hsdiv4_16fft_mcu_2_hsdivout1_clk",
117 "hsdiv4_16fft_mcu_2_hsdivout2_clk",
118 "hsdiv4_16fft_mcu_2_hsdivout3_clk",
119 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
120 "gluelogic_hfosc0_clkout",
121 "board_0_wkup_lf_clkin_out",
122};
123
124static const char * const main_pll4_xref_sel_out0_parents[] = {
125 "main_pll_hfosc_sel_out4",
126 "board_0_ext_refclk1_out",
127};
128
129static const char * const mcu_clkout_mux_out0_parents[] = {
130 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
131 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
132};
133
134static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
135 "main_pll_hfosc_sel_out0",
136 "hsdiv4_16fft_main_0_hsdivout0_clk",
137};
138
139static const char * const mcu_obsclk_outmux_out0_parents[] = {
140 "mcu_obsclk_div_out0",
141 "gluelogic_hfosc0_clkout",
142};
143
144static const char * const clkout_mux_out0_parents[] = {
145 "hsdiv4_16fft_main_3_hsdivout0_clk",
146 "hsdiv4_16fft_main_3_hsdivout0_clk",
147};
148
149static const char * const emmcsd_refclk_sel_out0_parents[] = {
150 "hsdiv4_16fft_main_0_hsdivout2_clk",
151 "hsdiv4_16fft_main_1_hsdivout2_clk",
152 "hsdiv4_16fft_main_3_hsdivout2_clk",
153 "hsdiv4_16fft_main_3_hsdivout2_clk",
154};
155
156static const char * const emmcsd_refclk_sel_out1_parents[] = {
157 "hsdiv4_16fft_main_0_hsdivout2_clk",
158 "hsdiv4_16fft_main_1_hsdivout2_clk",
159 "hsdiv4_16fft_main_3_hsdivout2_clk",
160 "hsdiv4_16fft_main_3_hsdivout2_clk",
161};
162
163static const char * const gtc_clk_mux_out0_parents[] = {
164 "hsdiv4_16fft_main_3_hsdivout1_clk",
165 "postdiv2_16fft_main_0_hsdivout6_clk",
166 "board_0_mcu_cpts0_rft_clk_out",
167 "board_0_cpts0_rft_clk_out",
168 "board_0_mcu_ext_refclk0_out",
169 "board_0_ext_refclk1_out",
170 NULL,
171 NULL,
172 NULL,
173 NULL,
174 NULL,
175 NULL,
176 NULL,
177 NULL,
178 "hsdiv4_16fft_mcu_2_hsdivout1_clk",
179 "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
180};
181
182static const char * const obsclk1_mux_out0_parents[] = {
183 NULL,
184 "hsdiv0_16fft_main_8_hsdivout0_clk",
185 NULL,
186 NULL,
187};
188
189static const char * const gpmc_fclk_sel_out0_parents[] = {
190 "hsdiv4_16fft_main_0_hsdivout3_clk",
191 "hsdiv4_16fft_main_2_hsdivout1_clk",
192 "hsdiv4_16fft_main_2_hsdivout1_clk",
193 "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
194};
195
196static const char * const audio_refclko_mux_out0_parents[] = {
197 NULL,
198 NULL,
199 NULL,
200 NULL,
201 NULL,
202 NULL,
203 NULL,
204 NULL,
205 NULL,
206 NULL,
207 NULL,
208 NULL,
209 NULL,
210 NULL,
211 NULL,
212 NULL,
213 NULL,
214 NULL,
215 NULL,
216 NULL,
217 NULL,
218 NULL,
219 NULL,
220 NULL,
221 NULL,
222 NULL,
223 NULL,
224 NULL,
225 "hsdiv2_16fft_main_4_hsdivout2_clk",
226 NULL,
227 NULL,
228 NULL,
229};
230
231static const char * const audio_refclko_mux_out1_parents[] = {
232 NULL,
233 NULL,
234 NULL,
235 NULL,
236 NULL,
237 NULL,
238 NULL,
239 NULL,
240 NULL,
241 NULL,
242 NULL,
243 NULL,
244 NULL,
245 NULL,
246 NULL,
247 NULL,
248 NULL,
249 NULL,
250 NULL,
251 NULL,
252 NULL,
253 NULL,
254 NULL,
255 NULL,
256 NULL,
257 NULL,
258 NULL,
259 NULL,
260 "hsdiv2_16fft_main_4_hsdivout2_clk",
261 NULL,
262 NULL,
263 NULL,
264};
265
266static const char * const obsclk0_mux_out0_parents[] = {
267 "hsdiv4_16fft_main_0_hsdivout0_clk",
268 "hsdiv4_16fft_main_1_hsdivout0_clk",
269 "hsdiv4_16fft_main_2_hsdivout0_clk",
270 "hsdiv4_16fft_main_3_hsdivout0_clk",
271 "hsdiv2_16fft_main_4_hsdivout0_clk",
272 NULL,
273 NULL,
274 NULL,
275 NULL,
276 NULL,
277 NULL,
278 NULL,
279 "hsdiv0_16fft_main_12_hsdivout0_clk",
280 "obsclk1_mux_out0",
281 "hsdiv1_16fft_main_14_hsdivout0_clk",
282 NULL,
283 NULL,
284 NULL,
285 NULL,
286 NULL,
287 NULL,
288 NULL,
289 NULL,
290 NULL,
291 NULL,
292 NULL,
293 NULL,
294 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
295 "board_0_wkup_lf_clkin_out",
296 "hsdiv4_16fft_main_0_hsdivout0_clk",
297 "board_0_hfosc1_clk_out",
298 "gluelogic_hfosc0_clkout",
299};
300
301static const struct clk_data clk_list[] = {
302 CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
303 CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
304 CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
305 CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
306 CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
307 CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
308 CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
309 CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
310 CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
311 CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
312 CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
313 CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
314 CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
315 CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
316 CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32550, 0),
317 CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
318 CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
319 CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
320 CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
321 CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
322 CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
323 CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
324 CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
325 CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
326 CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
327 CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
328 CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
329 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
330 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
331 CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666),
332 CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
333 CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
334 CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
335 CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
336 CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
337 CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
338 CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
339 CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
340 CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
341 CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
342 CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
343 CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
344 CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
345 CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
346 CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
347 CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
348 CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
349 CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
350 CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
351 CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0),
352 CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0),
353 CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
354 CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
355 CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
356 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0),
357 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0),
358 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0),
359 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
360 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
361 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
362 CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
363 CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
364 CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
365 CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
366 CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
367 CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
368 CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
369 CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
370 CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
371 CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
372 CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0),
373 CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
374 CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
375 CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
376 CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
377 CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
378 CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
379 CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
380 CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0),
381 CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
382 CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
383 CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
384 CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
385 CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
386 CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0),
387 CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0),
388 CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0),
389 CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
390 CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
391 CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
392 CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
393 CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0),
394 CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
395 CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
396 CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
397 CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
398 CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
399 CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
400 CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
401 CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
402 CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0),
403 CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0),
404 CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0),
405 CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0),
406 CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
407 CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0),
408 CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
409 CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
410};
411
412static const struct dev_clk soc_dev_clk_data[] = {
413 DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
414 DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
415 DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
416 DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
417 DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"),
418 DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
419 DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
420 DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
421 DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
422 DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
423 DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
424 DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
425 DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
426 DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
427 DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
428 DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
429 DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
430 DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
431 DEV_CLK(61, 1, "gtc_clk_mux_out0"),
432 DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
433 DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"),
434 DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
435 DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
436 DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
437 DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
438 DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
439 DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
440 DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
441 DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"),
442 DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"),
443 DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"),
444 DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
445 DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"),
446 DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
447 DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
448 DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"),
449 DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
450 DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
451 DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
452 DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
453 DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
454 DEV_CLK(102, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
455 DEV_CLK(102, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
456 DEV_CLK(102, 5, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
457 DEV_CLK(102, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
458 DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
459 DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
460 DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
461 DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
462 DEV_CLK(103, 4, "board_0_mcu_ospi0_dqs_out"),
463 DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"),
464 DEV_CLK(103, 6, "board_0_mcu_ospi0_dqs_out"),
465 DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
466 DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
467 DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
468 DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
469 DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
470 DEV_CLK(113, 0, "wkup_gpio0_clksel_out0"),
471 DEV_CLK(113, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
472 DEV_CLK(113, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
473 DEV_CLK(113, 3, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk"),
474 DEV_CLK(113, 4, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
475 DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
476 DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
477 DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
478 DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
479 DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"),
480 DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
481 DEV_CLK(149, 2, "mcuusart_clk_sel_out0"),
482 DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
483 DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"),
484 DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
485 DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
486 DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
487 DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
488 DEV_CLK(157, 5, "osbclk0_div_out0"),
489 DEV_CLK(157, 7, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
490 DEV_CLK(157, 14, "mcu_obsclk_outmux_out0"),
491 DEV_CLK(157, 15, "mcu_obsclk_div_out0"),
492 DEV_CLK(157, 16, "gluelogic_hfosc0_clkout"),
493 DEV_CLK(157, 35, "clkout_mux_out0"),
494 DEV_CLK(157, 36, "hsdiv4_16fft_main_3_hsdivout0_clk"),
495 DEV_CLK(157, 37, "hsdiv4_16fft_main_3_hsdivout0_clk"),
496 DEV_CLK(157, 38, "osbclk0_div_out0"),
497 DEV_CLK(157, 57, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
498 DEV_CLK(157, 65, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
499 DEV_CLK(157, 69, "mcu_clkout_mux_out0"),
500 DEV_CLK(157, 70, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
501 DEV_CLK(157, 71, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
502 DEV_CLK(157, 77, "audio_refclko_mux_out1"),
503 DEV_CLK(157, 106, "hsdiv2_16fft_main_4_hsdivout2_clk"),
504 DEV_CLK(157, 110, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
505 DEV_CLK(157, 114, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
506 DEV_CLK(157, 123, "mshsi2c_wkup_0_porscl"),
507 DEV_CLK(157, 131, "audio_refclko_mux_out0"),
508 DEV_CLK(157, 160, "hsdiv2_16fft_main_4_hsdivout2_clk"),
509 DEV_CLK(157, 169, "board_0_mcu_i2c0_scl_out"),
510 DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
511 DEV_CLK(157, 184, "gpmc_fclk_sel_out0"),
512 DEV_CLK(157, 187, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
513 DEV_CLK(157, 192, "osbclk0_div_out0"),
514 DEV_CLK(157, 193, "hsdiv4_16fft_main_0_hsdivout0_clk"),
515 DEV_CLK(157, 194, "hsdiv4_16fft_main_1_hsdivout0_clk"),
516 DEV_CLK(157, 195, "hsdiv4_16fft_main_2_hsdivout0_clk"),
517 DEV_CLK(157, 196, "hsdiv4_16fft_main_3_hsdivout0_clk"),
518 DEV_CLK(157, 197, "hsdiv2_16fft_main_4_hsdivout0_clk"),
519 DEV_CLK(157, 205, "hsdiv0_16fft_main_12_hsdivout0_clk"),
520 DEV_CLK(157, 206, "obsclk1_mux_out0"),
521 DEV_CLK(157, 207, "hsdiv1_16fft_main_14_hsdivout0_clk"),
522 DEV_CLK(157, 220, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
523 DEV_CLK(157, 221, "board_0_wkup_lf_clkin_out"),
524 DEV_CLK(157, 222, "hsdiv4_16fft_main_0_hsdivout0_clk"),
525 DEV_CLK(157, 223, "board_0_hfosc1_clk_out"),
526 DEV_CLK(157, 224, "gluelogic_hfosc0_clkout"),
527 DEV_CLK(197, 0, "board_0_wkup_i2c0_scl_out"),
528 DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"),
529 DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
530 DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
531 DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
532 DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
533 DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
534 DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
535 DEV_CLK(288, 12, "usb0_refclk_sel_out0"),
536 DEV_CLK(288, 13, "gluelogic_hfosc0_clkout"),
537 DEV_CLK(288, 14, "board_0_hfosc1_clk_out"),
538 DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
539 DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
540};
541
542const struct ti_k3_clk_platdata j7200_clk_platdata = {
543 .clk_list = clk_list,
544 .clk_list_cnt = 108,
545 .soc_dev_clk_data = soc_dev_clk_data,
546 .soc_dev_clk_data_cnt = 127,
547};