Simon Glass | 3a2f3bd | 2015-06-23 15:39:04 -0600 | [diff] [blame] | 1 | config RAM |
| 2 | bool "Enable RAM drivers using Driver Model" |
| 3 | depends on DM |
| 4 | help |
| 5 | This allows drivers to be provided for SDRAM and other RAM |
| 6 | controllers and their type to be specified in the board's device |
| 7 | tree. Generally some parameters are required to set up the RAM and |
| 8 | the RAM size can either be statically defined or dynamically |
| 9 | detected. |
| 10 | |
Masahiro Yamada | 2ba7a8c | 2015-08-12 07:31:48 +0900 | [diff] [blame] | 11 | config SPL_RAM |
Simon Glass | 3a2f3bd | 2015-06-23 15:39:04 -0600 | [diff] [blame] | 12 | bool "Enable RAM support in SPL" |
Philipp Tomsich | ce8d20c | 2017-06-29 01:41:52 +0200 | [diff] [blame] | 13 | depends on RAM && SPL_DM |
Simon Glass | 3a2f3bd | 2015-06-23 15:39:04 -0600 | [diff] [blame] | 14 | help |
| 15 | The RAM subsystem adds a small amount of overhead to the image. |
| 16 | If this is acceptable and you have a need to use RAM drivers in |
| 17 | SPL, enable this option. It might provide a cleaner interface to |
| 18 | setting up RAM (e.g. SDRAM / DDR) within SPL. |
Vikas Manocha | 2479609 | 2017-04-10 15:02:51 -0700 | [diff] [blame] | 19 | |
Philipp Tomsich | 6614f42 | 2017-06-29 01:42:40 +0200 | [diff] [blame] | 20 | config TPL_RAM |
Jagan Teki | 4361912 | 2017-08-25 20:16:00 +0530 | [diff] [blame] | 21 | bool "Enable RAM support in TPL" |
Tom Rini | 36a4ca0 | 2022-06-08 08:24:39 -0400 | [diff] [blame] | 22 | depends on RAM && TPL |
Philipp Tomsich | 6614f42 | 2017-06-29 01:42:40 +0200 | [diff] [blame] | 23 | help |
| 24 | The RAM subsystem adds a small amount of overhead to the image. |
| 25 | If this is acceptable and you have a need to use RAM drivers in |
| 26 | TPL, enable this option. It might provide a cleaner interface to |
| 27 | setting up RAM (e.g. SDRAM / DDR) within TPL. |
| 28 | |
Vikas Manocha | 2479609 | 2017-04-10 15:02:51 -0700 | [diff] [blame] | 29 | config STM32_SDRAM |
| 30 | bool "Enable STM32 SDRAM support" |
| 31 | depends on RAM |
| 32 | help |
| 33 | STM32F7 family devices support flexible memory controller(FMC) to |
| 34 | support external memories like sdram, psram & nand. |
| 35 | This driver is for the sdram memory interface with the FMC. |
Patrick Delaunay | 939d536 | 2018-03-12 10:46:11 +0100 | [diff] [blame] | 36 | |
Mario Six | 538b575 | 2018-08-06 10:23:30 +0200 | [diff] [blame] | 37 | config MPC83XX_SDRAM |
| 38 | bool "Enable MPC83XX SDRAM support" |
| 39 | depends on RAM |
| 40 | help |
| 41 | Enable support for the internal DDR Memory Controller of the MPC83xx |
| 42 | family of SoCs. Both static configurations, as well as configuring |
| 43 | the RAM through the use of SPD (Serial Presence Detect) is supported |
| 44 | via device tree settings. |
| 45 | |
Lokesh Vutla | c49bffb | 2018-11-02 19:51:02 +0530 | [diff] [blame] | 46 | config K3_AM654_DDRSS |
| 47 | bool "Enable AM654 DDRSS support" |
Andrew Davis | 1be5e97 | 2022-07-15 10:25:27 -0500 | [diff] [blame] | 48 | depends on RAM && SOC_K3_AM654 |
Lokesh Vutla | c49bffb | 2018-11-02 19:51:02 +0530 | [diff] [blame] | 49 | help |
| 50 | K3 based AM654 devices has DDR memory subsystem that comprises |
| 51 | Synopys DDR controller, Synopsis DDR phy and wrapper logic to |
| 52 | intergrate these blocks into the device. This DDR subsystem |
| 53 | provides an interface to external SDRAM devices. Enabling this |
| 54 | config add support for the initialization of the external |
| 55 | SDRAM devices connected to DDR subsystem. |
| 56 | |
Dave Gerlach | e777380 | 2021-05-11 10:22:10 -0500 | [diff] [blame] | 57 | config K3_DDRSS |
| 58 | bool "Enable K3 DDRSS support" |
| 59 | depends on RAM |
| 60 | |
| 61 | choice |
| 62 | depends on K3_DDRSS |
| 63 | prompt "K3 DDRSS Arch Support" |
| 64 | |
Apurva Nandan | 67ebc30 | 2024-02-24 01:51:41 +0530 | [diff] [blame] | 65 | default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 |
Dave Gerlach | 2c861a9 | 2021-05-11 10:22:12 -0500 | [diff] [blame] | 66 | default K3_AM64_DDRSS if SOC_K3_AM642 |
Suman Anna | 27fa412 | 2022-05-25 13:38:42 +0530 | [diff] [blame] | 67 | default K3_AM64_DDRSS if SOC_K3_AM625 |
Jayesh Choudhary | f68fb17 | 2024-06-12 14:41:17 +0530 | [diff] [blame] | 68 | default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S |
Dave Gerlach | 2c861a9 | 2021-05-11 10:22:12 -0500 | [diff] [blame] | 69 | |
Kevin Scholz | 521a4ef | 2019-10-07 19:26:36 +0530 | [diff] [blame] | 70 | config K3_J721E_DDRSS |
| 71 | bool "Enable J721E DDRSS support" |
Kevin Scholz | 521a4ef | 2019-10-07 19:26:36 +0530 | [diff] [blame] | 72 | help |
| 73 | The J721E DDR subsystem comprises DDR controller, DDR PHY and |
| 74 | wrapper logic to integrate these blocks in the device. The DDR |
| 75 | subsystem is used to provide an interface to external SDRAM |
| 76 | devices which can be utilized for storing program or data. |
| 77 | Enabling this config adds support for the DDR memory controller |
| 78 | on J721E family of SoCs. |
| 79 | |
Dave Gerlach | 2c861a9 | 2021-05-11 10:22:12 -0500 | [diff] [blame] | 80 | config K3_AM64_DDRSS |
| 81 | bool "Enable AM64 DDRSS support" |
| 82 | help |
| 83 | The AM64 DDR subsystem comprises DDR controller, DDR PHY and |
| 84 | wrapper logic to integrate these blocks in the device. The DDR |
| 85 | subsystem is used to provide an interface to external SDRAM |
| 86 | devices which can be utilized for storing program or data. |
| 87 | Enabling this config adds support for the DDR memory controller |
| 88 | on AM642 family of SoCs. |
| 89 | |
Bryan Brattlof | 85b5cc8 | 2022-10-24 16:53:28 -0500 | [diff] [blame] | 90 | config K3_AM62A_DDRSS |
| 91 | bool "Enable AM62A DDRSS support" |
| 92 | help |
| 93 | The AM62A DDR subsystem comprises of a DDR controller, DDR PHY and |
| 94 | wrapper logic to integrate these blocks into once device. The DDR |
| 95 | subsystem is used to provide an interface to external SDRAM devices |
| 96 | which can be utilized for storing programs or any other data. |
| 97 | Enabling this option adds support for the DDR memory controller for |
| 98 | the AM62A family of SoCs. |
| 99 | |
Dave Gerlach | e777380 | 2021-05-11 10:22:10 -0500 | [diff] [blame] | 100 | endchoice |
| 101 | |
Giulio Benetti | c513930 | 2020-01-10 15:51:44 +0100 | [diff] [blame] | 102 | config IMXRT_SDRAM |
| 103 | bool "Enable i.MXRT SDRAM support" |
| 104 | depends on RAM |
| 105 | help |
| 106 | i.MXRT family devices support smart external memory controller(SEMC) |
| 107 | to support external memories like sdram, psram & nand. |
| 108 | This driver is for the sdram memory interface with the SEMC. |
| 109 | |
Dylan Hung | f7d8f83 | 2020-09-07 16:25:07 +0800 | [diff] [blame] | 110 | source "drivers/ram/aspeed/Kconfig" |
Ralph Siemsen | 4ceb0d3 | 2023-05-12 21:36:53 -0400 | [diff] [blame] | 111 | source "drivers/ram/cadence/Kconfig" |
Andre Przywara | b652b69 | 2022-12-18 00:12:07 +0000 | [diff] [blame] | 112 | source "drivers/ram/octeon/Kconfig" |
Jagan Teki | 80442f9 | 2019-07-15 23:58:46 +0530 | [diff] [blame] | 113 | source "drivers/ram/rockchip/Kconfig" |
Pragnesh Patel | 4cefe72 | 2020-05-29 11:33:26 +0530 | [diff] [blame] | 114 | source "drivers/ram/sifive/Kconfig" |
Patrick Delaunay | 939d536 | 2018-03-12 10:46:11 +0100 | [diff] [blame] | 115 | source "drivers/ram/stm32mp1/Kconfig" |
Yanhong Wang | d60e880 | 2023-03-29 11:42:16 +0800 | [diff] [blame] | 116 | source "drivers/ram/starfive/Kconfig" |
Andre Przywara | b652b69 | 2022-12-18 00:12:07 +0000 | [diff] [blame] | 117 | source "drivers/ram/sunxi/Kconfig" |