blob: 64bffa3b181991ffdb8deb4ed35c534feb0c2a2e [file] [log] [blame]
Peng Fand69d0a62019-08-19 07:54:01 +00001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 NXP
4 */
5
Simon Glass0f2af882020-05-10 11:40:05 -06006#include <log.h>
Peng Fand69d0a62019-08-19 07:54:01 +00007#include <asm/io.h>
8#include <malloc.h>
9#include <clk-uclass.h>
10#include <dm/device.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070011#include <dm/devres.h>
Peng Fand69d0a62019-08-19 07:54:01 +000012#include <linux/clk-provider.h>
13#include <clk.h>
14#include "clk.h"
Simon Glassd66c5f72020-02-03 07:36:15 -070015#include <linux/err.h>
Peng Fand69d0a62019-08-19 07:54:01 +000016
17#define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
18
19#define PCG_PREDIV_SHIFT 16
20#define PCG_PREDIV_WIDTH 3
21#define PCG_PREDIV_MAX 8
22
23#define PCG_DIV_SHIFT 0
24#define PCG_DIV_WIDTH 6
25#define PCG_DIV_MAX 64
26
27#define PCG_PCS_SHIFT 24
28#define PCG_PCS_MASK 0x7
29
30#define PCG_CGC_SHIFT 28
31
32static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
33{
34 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
35 struct clk_composite *composite = (struct clk_composite *)clk->data;
36 ulong parent_rate = clk_get_parent_rate(&composite->clk);
37 unsigned long prediv_rate;
38 unsigned int prediv_value;
39 unsigned int div_value;
40
41 debug("%s: name %s prate: %lu reg: %p\n", __func__,
42 (&composite->clk)->dev->name, parent_rate, divider->reg);
43 prediv_value = readl(divider->reg) >> divider->shift;
44 prediv_value &= clk_div_mask(divider->width);
45
46 prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
47 NULL, divider->flags,
48 divider->width);
49
50 div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
51 div_value &= clk_div_mask(PCG_DIV_WIDTH);
52
53 return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
54 divider->flags, PCG_DIV_WIDTH);
55}
56
57static int imx8m_clk_composite_compute_dividers(unsigned long rate,
58 unsigned long parent_rate,
59 int *prediv, int *postdiv)
60{
61 int div1, div2;
62 int error = INT_MAX;
63 int ret = -EINVAL;
64
65 *prediv = 1;
66 *postdiv = 1;
67
68 for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
69 for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
70 int new_error = ((parent_rate / div1) / div2) - rate;
71
72 if (abs(new_error) < abs(error)) {
73 *prediv = div1;
74 *postdiv = div2;
75 error = new_error;
76 ret = 0;
77 }
78 }
79 }
80 return ret;
81}
82
83/*
84 * The clk are bound to a dev, because it is part of composite clk
85 * use composite clk to get dev
86 */
87static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
88 unsigned long rate)
89{
90 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
91 struct clk_composite *composite = (struct clk_composite *)clk->data;
92 ulong parent_rate = clk_get_parent_rate(&composite->clk);
93 int prediv_value;
94 int div_value;
95 int ret;
96 u32 val;
97
98 ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
99 &prediv_value, &div_value);
100 if (ret)
101 return ret;
102
103 val = readl(divider->reg);
104 val &= ~((clk_div_mask(divider->width) << divider->shift) |
105 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
106
107 val |= (u32)(prediv_value - 1) << divider->shift;
108 val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
109 writel(val, divider->reg);
110
111 return clk_get_rate(&composite->clk);
112}
113
114static const struct clk_ops imx8m_clk_composite_divider_ops = {
115 .get_rate = imx8m_clk_composite_divider_recalc_rate,
116 .set_rate = imx8m_clk_composite_divider_set_rate,
117};
118
Michael Trimarchic09a2c02024-07-05 09:19:52 +0200119static int imx8m_clk_mux_set_parent(struct clk *clk, struct clk *parent)
120{
121 struct clk_mux *mux = to_clk_mux(clk);
122 int index;
123 u32 val;
124 u32 reg;
125
126 index = clk_mux_fetch_parent_index(clk, parent);
127 if (index < 0) {
128 log_err("Could not fetch index\n");
129 return index;
130 }
131
132 val = clk_mux_index_to_val(mux->table, mux->flags, index);
133
134 reg = readl(mux->reg);
135 reg &= ~(mux->mask << mux->shift);
136 val = val << mux->shift;
137 reg |= val;
138
139 /*
140 * write twice to make sure non-target interface
141 * SEL_A/B point the same clk input.
142 */
143 writel(reg, mux->reg);
144 writel(reg, mux->reg);
145
146 return 0;
147}
148
149const struct clk_ops imx8m_clk_mux_ops = {
150 .get_rate = clk_generic_get_rate,
151 .set_parent = imx8m_clk_mux_set_parent,
152};
153
Peng Fand69d0a62019-08-19 07:54:01 +0000154struct clk *imx8m_clk_composite_flags(const char *name,
155 const char * const *parent_names,
156 int num_parents, void __iomem *reg,
157 unsigned long flags)
158{
159 struct clk *clk = ERR_PTR(-ENOMEM);
160 struct clk_divider *div = NULL;
161 struct clk_gate *gate = NULL;
162 struct clk_mux *mux = NULL;
163
164 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
165 if (!mux)
166 goto fail;
167
168 mux->reg = reg;
169 mux->shift = PCG_PCS_SHIFT;
170 mux->mask = PCG_PCS_MASK;
171 mux->num_parents = num_parents;
Peng Fand69d0a62019-08-19 07:54:01 +0000172 mux->parent_names = parent_names;
173
174 div = kzalloc(sizeof(*div), GFP_KERNEL);
175 if (!div)
176 goto fail;
177
178 div->reg = reg;
179 div->shift = PCG_PREDIV_SHIFT;
180 div->width = PCG_PREDIV_WIDTH;
Michael Trimarchia1d6ea82024-07-02 12:26:17 +0200181 div->flags = CLK_DIVIDER_ROUND_CLOSEST;
Peng Fand69d0a62019-08-19 07:54:01 +0000182
183 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
184 if (!gate)
185 goto fail;
186
187 gate->reg = reg;
188 gate->bit_idx = PCG_CGC_SHIFT;
Peng Fand69d0a62019-08-19 07:54:01 +0000189
190 clk = clk_register_composite(NULL, name,
191 parent_names, num_parents,
Michael Trimarchic09a2c02024-07-05 09:19:52 +0200192 &mux->clk, &imx8m_clk_mux_ops, &div->clk,
Peng Fand69d0a62019-08-19 07:54:01 +0000193 &imx8m_clk_composite_divider_ops,
194 &gate->clk, &clk_gate_ops, flags);
195 if (IS_ERR(clk))
196 goto fail;
197
198 return clk;
199
200fail:
201 kfree(gate);
202 kfree(div);
203 kfree(mux);
204 return ERR_CAST(clk);
205}