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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm64 / ti / k3-am65-mcu.dtsi
blob: 6ff3ccc39fb448c4ca9fd642740ff77bb20b558b [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only OR MIT
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2/*
3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals
4 *
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]6 */
7
8&cbass_mcu {
9 mcu_conf: scm-conf@40f00000 {
10 compatible = "syscon", "simple-mfd";
11 reg = <0x0 0x40f00000 0x0 0x20000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
15
16 phy_gmii_sel: phy@4040 {
17 compatible = "ti,am654-phy-gmii-sel";
18 reg = <0x4040 0x4>;
19 #phy-cells = <1>;
20 };
21 };
22
23 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
24 mcu_timerio_input: pinctrl@40f04200 {
25 compatible = "pinctrl-single";
26 reg = <0x0 0x40f04200 0x0 0x10>;
27 #pinctrl-cells = <1>;
28 pinctrl-single,register-width = <32>;
29 pinctrl-single,function-mask = <0x00000101>;
30 };
31
32 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
33 mcu_timerio_output: pinctrl@40f04280 {
34 compatible = "pinctrl-single";
35 reg = <0x0 0x40f04280 0x0 0x8>;
36 #pinctrl-cells = <1>;
37 pinctrl-single,register-width = <32>;
38 pinctrl-single,function-mask = <0x00000003>;
39 };
40
41 mcu_uart0: serial@40a00000 {
42 compatible = "ti,am654-uart";
43 reg = <0x00 0x40a00000 0x00 0x100>;
44 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
45 clock-frequency = <96000000>;
46 current-speed = <115200>;
47 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
48 status = "disabled";
49 };
50
51 mcu_ram: sram@41c00000 {
52 compatible = "mmio-sram";
53 reg = <0x00 0x41c00000 0x00 0x80000>;
54 ranges = <0x0 0x00 0x41c00000 0x80000>;
55 #address-cells = <1>;
56 #size-cells = <1>;
57 };
58
59 mcu_i2c0: i2c@40b00000 {
60 compatible = "ti,am654-i2c", "ti,omap4-i2c";
61 reg = <0x0 0x40b00000 0x0 0x100>;
62 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 clock-names = "fck";
66 clocks = <&k3_clks 114 1>;
67 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
68 status = "disabled";
69 };
70
71 mcu_spi0: spi@40300000 {
72 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
73 reg = <0x0 0x40300000 0x0 0x400>;
74 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
75 clocks = <&k3_clks 142 1>;
76 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
77 #address-cells = <1>;
78 #size-cells = <0>;
79 status = "disabled";
80 };
81
82 mcu_spi1: spi@40310000 {
83 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
84 reg = <0x0 0x40310000 0x0 0x400>;
85 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&k3_clks 143 1>;
87 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
88 #address-cells = <1>;
89 #size-cells = <0>;
90 status = "disabled";
91 };
92
93 mcu_spi2: spi@40320000 {
94 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
95 reg = <0x0 0x40320000 0x0 0x400>;
96 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&k3_clks 144 1>;
98 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
99 #address-cells = <1>;
100 #size-cells = <0>;
101 status = "disabled";
102 };
103
104 tscadc0: tscadc@40200000 {
105 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
106 reg = <0x0 0x40200000 0x0 0x1000>;
107 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&k3_clks 0 2>;
109 assigned-clocks = <&k3_clks 0 2>;
110 assigned-clock-rates = <60000000>;
111 clock-names = "fck";
112 dmas = <&mcu_udmap 0x7100>,
113 <&mcu_udmap 0x7101 >;
114 dma-names = "fifo0", "fifo1";
115 status = "disabled";
116
117 adc {
118 #io-channel-cells = <1>;
119 compatible = "ti,am654-adc", "ti,am3359-adc";
120 };
121 };
122
123 tscadc1: tscadc@40210000 {
124 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
125 reg = <0x0 0x40210000 0x0 0x1000>;
126 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&k3_clks 1 2>;
128 assigned-clocks = <&k3_clks 1 2>;
129 assigned-clock-rates = <60000000>;
130 clock-names = "fck";
131 dmas = <&mcu_udmap 0x7102>,
132 <&mcu_udmap 0x7103>;
133 dma-names = "fifo0", "fifo1";
134 status = "disabled";
135
136 adc {
137 #io-channel-cells = <1>;
138 compatible = "ti,am654-adc", "ti,am3359-adc";
139 };
140 };
141
142 /*
143 * The MCU domain timer interrupts are routed only to the ESM module,
144 * and not currently available for Linux. The MCU domain timers are
145 * of limited use without interrupts, and likely reserved by the ESM.
146 */
147 mcu_timer0: timer@40400000 {
148 compatible = "ti,am654-timer";
149 reg = <0x00 0x40400000 0x00 0x400>;
150 clocks = <&k3_clks 35 0>;
151 clock-names = "fck";
152 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
153 ti,timer-pwm;
154 status = "reserved";
155 };
156
157 mcu_timer1: timer@40410000 {
158 compatible = "ti,am654-timer";
159 reg = <0x00 0x40410000 0x00 0x400>;
160 clocks = <&k3_clks 36 0>;
161 clock-names = "fck";
162 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
163 ti,timer-pwm;
164 status = "reserved";
165 };
166
167 mcu_timer2: timer@40420000 {
168 compatible = "ti,am654-timer";
169 reg = <0x00 0x40420000 0x00 0x400>;
170 clocks = <&k3_clks 37 0>;
171 clock-names = "fck";
172 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
173 ti,timer-pwm;
174 status = "reserved";
175 };
176
177 mcu_timer3: timer@40430000 {
178 compatible = "ti,am654-timer";
179 reg = <0x00 0x40430000 0x00 0x400>;
180 clocks = <&k3_clks 38 0>;
181 clock-names = "fck";
182 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
183 ti,timer-pwm;
184 status = "reserved";
185 };
186
187 mcu_navss: bus@28380000 {
188 compatible = "simple-bus";
189 #address-cells = <2>;
190 #size-cells = <2>;
191 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
192 dma-coherent;
193 dma-ranges;
194
195 ti,sci-dev-id = <119>;
196
197 mcu_ringacc: ringacc@2b800000 {
198 compatible = "ti,am654-navss-ringacc";
199 reg = <0x0 0x2b800000 0x0 0x400000>,
200 <0x0 0x2b000000 0x0 0x400000>,
201 <0x0 0x28590000 0x0 0x100>,
202 <0x0 0x2a500000 0x0 0x40000>,
203 <0x0 0x28440000 0x0 0x40000>;
204 reg-names = "rt", "fifos", "proxy_gcfg",
205 "proxy_target", "cfg";
206 ti,num-rings = <286>;
207 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
208 ti,sci = <&dmsc>;
209 ti,sci-dev-id = <195>;
210 msi-parent = <&inta_main_udmass>;
211 };
212
213 mcu_udmap: dma-controller@285c0000 {
214 compatible = "ti,am654-navss-mcu-udmap";
215 reg = <0x0 0x285c0000 0x0 0x100>,
216 <0x0 0x2a800000 0x0 0x40000>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]217 <0x0 0x2aa00000 0x0 0x40000>,
218 <0x0 0x284a0000 0x0 0x4000>,
219 <0x0 0x284c0000 0x0 0x4000>,
220 <0x0 0x28400000 0x0 0x2000>;
221 reg-names = "gcfg", "rchanrt", "tchanrt",
222 "tchan", "rchan", "rflow";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]223 msi-parent = <&inta_main_udmass>;
224 #dma-cells = <1>;
225
226 ti,sci = <&dmsc>;
227 ti,sci-dev-id = <194>;
228 ti,ringacc = <&mcu_ringacc>;
229
230 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
231 <0xd>; /* TX_CHAN */
232 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
233 <0xa>; /* RX_CHAN */
234 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
235 };
236 };
237
238 secure_proxy_mcu: mailbox@2a480000 {
239 compatible = "ti,am654-secure-proxy";
240 #mbox-cells = <1>;
241 reg-names = "target_data", "rt", "scfg";
242 reg = <0x0 0x2a480000 0x0 0x80000>,
243 <0x0 0x2a380000 0x0 0x80000>,
244 <0x0 0x2a400000 0x0 0x80000>;
245 /*
246 * Marked Disabled:
247 * Node is incomplete as it is meant for bootloaders and
248 * firmware on non-MPU processors
249 */
250 status = "disabled";
251 };
252
253 m_can0: can@40528000 {
254 compatible = "bosch,m_can";
255 reg = <0x0 0x40528000 0x0 0x400>,
256 <0x0 0x40500000 0x0 0x4400>;
257 reg-names = "m_can", "message_ram";
258 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
259 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
260 clock-names = "hclk", "cclk";
261 interrupt-parent = <&gic500>;
262 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
264 interrupt-names = "int0", "int1";
265 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
266 status = "disabled";
267 };
268
269 m_can1: can@40568000 {
270 compatible = "bosch,m_can";
271 reg = <0x0 0x40568000 0x0 0x400>,
272 <0x0 0x40540000 0x0 0x4400>;
273 reg-names = "m_can", "message_ram";
274 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
275 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
276 clock-names = "hclk", "cclk";
277 interrupt-parent = <&gic500>;
278 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "int0", "int1";
281 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
282 status = "disabled";
283 };
284
285 fss: bus@47000000 {
286 compatible = "simple-bus";
287 #address-cells = <2>;
288 #size-cells = <2>;
289 ranges;
290
291 ospi0: spi@47040000 {
292 compatible = "ti,am654-ospi", "cdns,qspi-nor";
293 reg = <0x0 0x47040000 0x0 0x100>,
294 <0x5 0x00000000 0x1 0x0000000>;
295 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
296 cdns,fifo-depth = <256>;
297 cdns,fifo-width = <4>;
298 cdns,trigger-address = <0x0>;
299 clocks = <&k3_clks 248 0>;
300 assigned-clocks = <&k3_clks 248 0>;
301 assigned-clock-parents = <&k3_clks 248 2>;
302 assigned-clock-rates = <166666666>;
303 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
304 #address-cells = <1>;
305 #size-cells = <0>;
306 status = "disabled";
307 };
308
309 ospi1: spi@47050000 {
310 compatible = "ti,am654-ospi", "cdns,qspi-nor";
311 reg = <0x0 0x47050000 0x0 0x100>,
312 <0x7 0x00000000 0x1 0x00000000>;
313 interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
314 cdns,fifo-depth = <256>;
315 cdns,fifo-width = <4>;
316 cdns,trigger-address = <0x0>;
317 clocks = <&k3_clks 249 6>;
318 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 status = "disabled";
322 };
323 };
324
325 mcu_cpsw: ethernet@46000000 {
326 compatible = "ti,am654-cpsw-nuss";
327 #address-cells = <2>;
328 #size-cells = <2>;
329 reg = <0x0 0x46000000 0x0 0x200000>;
330 reg-names = "cpsw_nuss";
331 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
332 dma-coherent;
333 clocks = <&k3_clks 5 10>;
334 clock-names = "fck";
335 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
336
337 dmas = <&mcu_udmap 0xf000>,
338 <&mcu_udmap 0xf001>,
339 <&mcu_udmap 0xf002>,
340 <&mcu_udmap 0xf003>,
341 <&mcu_udmap 0xf004>,
342 <&mcu_udmap 0xf005>,
343 <&mcu_udmap 0xf006>,
344 <&mcu_udmap 0xf007>,
345 <&mcu_udmap 0x7000>;
346 dma-names = "tx0", "tx1", "tx2", "tx3",
347 "tx4", "tx5", "tx6", "tx7",
348 "rx";
349
350 ethernet-ports {
351 #address-cells = <1>;
352 #size-cells = <0>;
353
354 cpsw_port1: port@1 {
355 reg = <1>;
356 ti,mac-only;
357 label = "port1";
358 ti,syscon-efuse = <&mcu_conf 0x200>;
359 phys = <&phy_gmii_sel 1>;
360 };
361 };
362
363 davinci_mdio: mdio@f00 {
364 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
365 reg = <0x0 0xf00 0x0 0x100>;
366 #address-cells = <1>;
367 #size-cells = <0>;
368 clocks = <&k3_clks 5 10>;
369 clock-names = "fck";
370 bus_freq = <1000000>;
371 status = "disabled";
372 };
373
374 cpts@3d000 {
375 compatible = "ti,am65-cpts";
376 reg = <0x0 0x3d000 0x0 0x400>;
377 clocks = <&mcu_cpsw_cpts_mux>;
378 clock-names = "cpts";
379 interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-names = "cpts";
381 ti,cpts-ext-ts-inputs = <4>;
382 ti,cpts-periodic-outputs = <2>;
383
384 mcu_cpsw_cpts_mux: refclk-mux {
385 #clock-cells = <0>;
386 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
387 <&k3_clks 118 6>, <&k3_clks 118 3>,
388 <&k3_clks 118 8>, <&k3_clks 118 14>,
389 <&k3_clks 120 3>, <&k3_clks 121 3>;
390 assigned-clocks = <&mcu_cpsw_cpts_mux>;
391 assigned-clock-parents = <&k3_clks 118 5>;
392 };
393 };
394 };
395
396 mcu_r5fss0: r5fss@41000000 {
397 compatible = "ti,am654-r5fss";
398 ti,cluster-mode = <1>;
399 #address-cells = <1>;
400 #size-cells = <1>;
401 ranges = <0x41000000 0x00 0x41000000 0x20000>,
402 <0x41400000 0x00 0x41400000 0x20000>;
403 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
404
405 mcu_r5fss0_core0: r5f@41000000 {
406 compatible = "ti,am654-r5f";
407 reg = <0x41000000 0x00008000>,
408 <0x41010000 0x00008000>;
409 reg-names = "atcm", "btcm";
410 ti,sci = <&dmsc>;
411 ti,sci-dev-id = <159>;
412 ti,sci-proc-ids = <0x01 0xff>;
413 resets = <&k3_reset 159 1>;
414 firmware-name = "am65x-mcu-r5f0_0-fw";
415 ti,atcm-enable = <1>;
416 ti,btcm-enable = <1>;
417 ti,loczrama = <1>;
418 };
419
420 mcu_r5fss0_core1: r5f@41400000 {
421 compatible = "ti,am654-r5f";
422 reg = <0x41400000 0x00008000>,
423 <0x41410000 0x00008000>;
424 reg-names = "atcm", "btcm";
425 ti,sci = <&dmsc>;
426 ti,sci-dev-id = <245>;
427 ti,sci-proc-ids = <0x02 0xff>;
428 resets = <&k3_reset 245 1>;
429 firmware-name = "am65x-mcu-r5f0_1-fw";
430 ti,atcm-enable = <1>;
431 ti,btcm-enable = <1>;
432 ti,loczrama = <1>;
433 };
434 };
435
436 mcu_rti1: watchdog@40610000 {
437 compatible = "ti,j7-rti-wdt";
438 reg = <0x0 0x40610000 0x0 0x100>;
439 clocks = <&k3_clks 135 0>;
440 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
441 assigned-clocks = <&k3_clks 135 0>;
442 assigned-clock-parents = <&k3_clks 135 4>;
443 };
444};