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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm64 / ti / k3-am65-main.dtsi
blob: ff857117d71937b132468ceb915500eb533fcb9a [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only OR MIT
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2/*
3 * Device Tree Source for AM6 SoC Family Main Domain peripherals
4 *
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]6 */
7#include <dt-bindings/phy/phy-am654-serdes.h>
8
9&cbass_main {
10 msmc_ram: sram@70000000 {
11 compatible = "mmio-sram";
12 reg = <0x0 0x70000000 0x0 0x200000>;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
16
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
19 };
20
21 sysfw-sram@f0000 {
22 reg = <0xf0000 0x10000>;
23 };
24
25 l3cache-sram@100000 {
26 reg = <0x100000 0x100000>;
27 };
28 };
29
30 gic500: interrupt-controller@1800000 {
31 compatible = "arm,gic-v3";
32 #address-cells = <2>;
33 #size-cells = <2>;
34 ranges;
35 #interrupt-cells = <3>;
36 interrupt-controller;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
42 /*
43 * vcpumntirq:
44 * virtual CPU interface maintenance interrupt
45 */
46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
47
48 gic_its: msi-controller@1820000 {
49 compatible = "arm,gic-v3-its";
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
52 msi-controller;
53 #msi-cells = <1>;
54 };
55 };
56
57 serdes0: serdes@900000 {
58 compatible = "ti,phy-am654-serdes";
59 reg = <0x0 0x900000 0x0 0x2000>;
60 reg-names = "serdes";
61 #phy-cells = <2>;
62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
67 ti,serdes-clk = <&serdes0_clk>;
68 #clock-cells = <1>;
69 mux-controls = <&serdes_mux 0>;
70 };
71
72 serdes1: serdes@910000 {
73 compatible = "ti,phy-am654-serdes";
74 reg = <0x0 0x910000 0x0 0x2000>;
75 reg-names = "serdes";
76 #phy-cells = <2>;
77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
82 ti,serdes-clk = <&serdes1_clk>;
83 #clock-cells = <1>;
84 mux-controls = <&serdes_mux 1>;
85 };
86
87 main_uart0: serial@2800000 {
88 compatible = "ti,am654-uart";
89 reg = <0x00 0x02800000 0x00 0x100>;
90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
91 clock-frequency = <48000000>;
92 current-speed = <115200>;
93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
94 status = "disabled";
95 };
96
97 main_uart1: serial@2810000 {
98 compatible = "ti,am654-uart";
99 reg = <0x00 0x02810000 0x00 0x100>;
100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
101 clock-frequency = <48000000>;
102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
103 status = "disabled";
104 };
105
106 main_uart2: serial@2820000 {
107 compatible = "ti,am654-uart";
108 reg = <0x00 0x02820000 0x00 0x100>;
109 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
110 clock-frequency = <48000000>;
111 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
112 status = "disabled";
113 };
114
115 crypto: crypto@4e00000 {
116 compatible = "ti,am654-sa2ul";
117 reg = <0x0 0x4e00000 0x0 0x1200>;
118 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
119 #address-cells = <2>;
120 #size-cells = <2>;
121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
122
123 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
124 <&main_udmap 0x4003>;
125 dma-names = "tx", "rx1", "rx2";
126
127 rng: rng@4e10000 {
128 compatible = "inside-secure,safexcel-eip76";
129 reg = <0x0 0x4e10000 0x0 0x7d>;
130 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
131 status = "disabled"; /* Used by OP-TEE */
132 };
133 };
134
135 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
136 main_timerio_input: pinctrl@104200 {
137 compatible = "pinctrl-single";
138 reg = <0x0 0x104200 0x0 0x30>;
139 #pinctrl-cells = <1>;
140 pinctrl-single,register-width = <32>;
141 pinctrl-single,function-mask = <0x0000001ff>;
142 };
143
144 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
145 main_timerio_output: pinctrl@104280 {
146 compatible = "pinctrl-single";
147 reg = <0x0 0x104280 0x0 0x20>;
148 #pinctrl-cells = <1>;
149 pinctrl-single,register-width = <32>;
150 pinctrl-single,function-mask = <0x0000000f>;
151 };
152
153 main_pmx0: pinctrl@11c000 {
154 compatible = "pinctrl-single";
155 reg = <0x0 0x11c000 0x0 0x2e4>;
156 #pinctrl-cells = <1>;
157 pinctrl-single,register-width = <32>;
158 pinctrl-single,function-mask = <0xffffffff>;
159 };
160
161 main_pmx1: pinctrl@11c2e8 {
162 compatible = "pinctrl-single";
163 reg = <0x0 0x11c2e8 0x0 0x24>;
164 #pinctrl-cells = <1>;
165 pinctrl-single,register-width = <32>;
166 pinctrl-single,function-mask = <0xffffffff>;
167 };
168
169 main_i2c0: i2c@2000000 {
170 compatible = "ti,am654-i2c", "ti,omap4-i2c";
171 reg = <0x0 0x2000000 0x0 0x100>;
172 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 clock-names = "fck";
176 clocks = <&k3_clks 110 1>;
177 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
178 status = "disabled";
179 };
180
181 main_i2c1: i2c@2010000 {
182 compatible = "ti,am654-i2c", "ti,omap4-i2c";
183 reg = <0x0 0x2010000 0x0 0x100>;
184 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 clock-names = "fck";
188 clocks = <&k3_clks 111 1>;
189 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
190 status = "disabled";
191 };
192
193 main_i2c2: i2c@2020000 {
194 compatible = "ti,am654-i2c", "ti,omap4-i2c";
195 reg = <0x0 0x2020000 0x0 0x100>;
196 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 clock-names = "fck";
200 clocks = <&k3_clks 112 1>;
201 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
202 status = "disabled";
203 };
204
205 main_i2c3: i2c@2030000 {
206 compatible = "ti,am654-i2c", "ti,omap4-i2c";
207 reg = <0x0 0x2030000 0x0 0x100>;
208 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 clock-names = "fck";
212 clocks = <&k3_clks 113 1>;
213 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
214 status = "disabled";
215 };
216
217 ecap0: pwm@3100000 {
218 compatible = "ti,am654-ecap", "ti,am3352-ecap";
219 #pwm-cells = <3>;
220 reg = <0x0 0x03100000 0x0 0x60>;
221 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
222 clocks = <&k3_clks 39 0>;
223 clock-names = "fck";
224 status = "disabled";
225 };
226
227 main_spi0: spi@2100000 {
228 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
229 reg = <0x0 0x2100000 0x0 0x400>;
230 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&k3_clks 137 1>;
232 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
236 dma-names = "tx0", "rx0";
237 status = "disabled";
238 };
239
240 main_spi1: spi@2110000 {
241 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
242 reg = <0x0 0x2110000 0x0 0x400>;
243 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&k3_clks 138 1>;
245 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 assigned-clocks = <&k3_clks 137 1>;
249 assigned-clock-rates = <48000000>;
250 status = "disabled";
251 };
252
253 main_spi2: spi@2120000 {
254 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
255 reg = <0x0 0x2120000 0x0 0x400>;
256 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&k3_clks 139 1>;
258 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 status = "disabled";
262 };
263
264 main_spi3: spi@2130000 {
265 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
266 reg = <0x0 0x2130000 0x0 0x400>;
267 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&k3_clks 140 1>;
269 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
270 #address-cells = <1>;
271 #size-cells = <0>;
272 status = "disabled";
273 };
274
275 main_spi4: spi@2140000 {
276 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
277 reg = <0x0 0x2140000 0x0 0x400>;
278 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&k3_clks 141 1>;
280 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 status = "disabled";
284 };
285
286 main_timer0: timer@2400000 {
287 compatible = "ti,am654-timer";
288 reg = <0x00 0x2400000 0x00 0x400>;
289 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&k3_clks 23 0>;
291 clock-names = "fck";
292 assigned-clocks = <&k3_clks 23 0>;
293 assigned-clock-parents = <&k3_clks 23 1>;
294 power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
295 ti,timer-pwm;
296 };
297
298 main_timer1: timer@2410000 {
299 compatible = "ti,am654-timer";
300 reg = <0x00 0x2410000 0x00 0x400>;
301 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&k3_clks 24 0>;
303 clock-names = "fck";
304 assigned-clocks = <&k3_clks 24 0>;
305 assigned-clock-parents = <&k3_clks 24 1>;
306 power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
307 ti,timer-pwm;
308 };
309
310 main_timer2: timer@2420000 {
311 compatible = "ti,am654-timer";
312 reg = <0x00 0x2420000 0x00 0x400>;
313 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&k3_clks 27 0>;
315 clock-names = "fck";
316 assigned-clocks = <&k3_clks 27 0>;
317 assigned-clock-parents = <&k3_clks 27 1>;
318 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
319 ti,timer-pwm;
320 };
321
322 main_timer3: timer@2430000 {
323 compatible = "ti,am654-timer";
324 reg = <0x00 0x2430000 0x00 0x400>;
325 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&k3_clks 28 0>;
327 clock-names = "fck";
328 assigned-clocks = <&k3_clks 28 0>;
329 assigned-clock-parents = <&k3_clks 28 1>;
330 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
331 ti,timer-pwm;
332 };
333
334 main_timer4: timer@2440000 {
335 compatible = "ti,am654-timer";
336 reg = <0x00 0x2440000 0x00 0x400>;
337 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&k3_clks 29 0>;
339 clock-names = "fck";
340 assigned-clocks = <&k3_clks 29 0>;
341 assigned-clock-parents = <&k3_clks 29 1>;
342 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
343 ti,timer-pwm;
344 };
345
346 main_timer5: timer@2450000 {
347 compatible = "ti,am654-timer";
348 reg = <0x00 0x2450000 0x00 0x400>;
349 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&k3_clks 30 0>;
351 clock-names = "fck";
352 assigned-clocks = <&k3_clks 30 0>;
353 assigned-clock-parents = <&k3_clks 30 1>;
354 power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
355 ti,timer-pwm;
356 };
357
358 main_timer6: timer@2460000 {
359 compatible = "ti,am654-timer";
360 reg = <0x00 0x2460000 0x00 0x400>;
361 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&k3_clks 31 0>;
363 assigned-clocks = <&k3_clks 31 0>;
364 assigned-clock-parents = <&k3_clks 31 1>;
365 clock-names = "fck";
366 power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
367 ti,timer-pwm;
368 };
369
370 main_timer7: timer@2470000 {
371 compatible = "ti,am654-timer";
372 reg = <0x00 0x2470000 0x00 0x400>;
373 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&k3_clks 32 0>;
375 clock-names = "fck";
376 assigned-clocks = <&k3_clks 32 0>;
377 assigned-clock-parents = <&k3_clks 32 1>;
378 power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
379 ti,timer-pwm;
380 };
381
382 main_timer8: timer@2480000 {
383 compatible = "ti,am654-timer";
384 reg = <0x00 0x2480000 0x00 0x400>;
385 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&k3_clks 33 0>;
387 clock-names = "fck";
388 assigned-clocks = <&k3_clks 33 0>;
389 assigned-clock-parents = <&k3_clks 33 1>;
390 power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
391 ti,timer-pwm;
392 };
393
394 main_timer9: timer@2490000 {
395 compatible = "ti,am654-timer";
396 reg = <0x00 0x2490000 0x00 0x400>;
397 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&k3_clks 34 0>;
399 clock-names = "fck";
400 assigned-clocks = <&k3_clks 34 0>;
401 assigned-clock-parents = <&k3_clks 34 1>;
402 power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
403 ti,timer-pwm;
404 };
405
406 main_timer10: timer@24a0000 {
407 compatible = "ti,am654-timer";
408 reg = <0x00 0x24a0000 0x00 0x400>;
409 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&k3_clks 25 0>;
411 clock-names = "fck";
412 assigned-clocks = <&k3_clks 25 0>;
413 assigned-clock-parents = <&k3_clks 25 1>;
414 power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
415 ti,timer-pwm;
416 };
417
418 main_timer11: timer@24b0000 {
419 compatible = "ti,am654-timer";
420 reg = <0x00 0x24b0000 0x00 0x400>;
421 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&k3_clks 26 0>;
423 clock-names = "fck";
424 assigned-clocks = <&k3_clks 26 0>;
425 assigned-clock-parents = <&k3_clks 26 1>;
426 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
427 ti,timer-pwm;
428 };
429
430 sdhci0: mmc@4f80000 {
431 compatible = "ti,am654-sdhci-5.1";
432 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
433 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
434 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
435 clock-names = "clk_ahb", "clk_xin";
436 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
437 mmc-ddr-1_8v;
438 mmc-hs200-1_8v;
439 ti,otap-del-sel-legacy = <0x0>;
440 ti,otap-del-sel-mmc-hs = <0x0>;
441 ti,otap-del-sel-sd-hs = <0x0>;
442 ti,otap-del-sel-sdr12 = <0x0>;
443 ti,otap-del-sel-sdr25 = <0x0>;
444 ti,otap-del-sel-sdr50 = <0x8>;
445 ti,otap-del-sel-sdr104 = <0x7>;
446 ti,otap-del-sel-ddr50 = <0x5>;
447 ti,otap-del-sel-ddr52 = <0x5>;
448 ti,otap-del-sel-hs200 = <0x5>;
449 ti,otap-del-sel-hs400 = <0x0>;
450 ti,trm-icp = <0x8>;
451 dma-coherent;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]452 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]453 };
454
455 sdhci1: mmc@4fa0000 {
456 compatible = "ti,am654-sdhci-5.1";
457 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
458 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
459 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
460 clock-names = "clk_ahb", "clk_xin";
461 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
462 ti,otap-del-sel-legacy = <0x0>;
463 ti,otap-del-sel-mmc-hs = <0x0>;
464 ti,otap-del-sel-sd-hs = <0x0>;
465 ti,otap-del-sel-sdr12 = <0x0>;
466 ti,otap-del-sel-sdr25 = <0x0>;
467 ti,otap-del-sel-sdr50 = <0x8>;
468 ti,otap-del-sel-sdr104 = <0x7>;
469 ti,otap-del-sel-ddr50 = <0x4>;
470 ti,otap-del-sel-ddr52 = <0x4>;
471 ti,otap-del-sel-hs200 = <0x7>;
472 ti,clkbuf-sel = <0x7>;
473 ti,trm-icp = <0x8>;
474 dma-coherent;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]475 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]476 };
477
478 scm_conf: scm-conf@100000 {
479 compatible = "syscon", "simple-mfd";
480 reg = <0 0x00100000 0 0x1c000>;
481 #address-cells = <1>;
482 #size-cells = <1>;
483 ranges = <0x0 0x0 0x00100000 0x1c000>;
484
485 serdes0_clk: clock@4080 {
486 compatible = "syscon";
487 reg = <0x00004080 0x4>;
488 };
489
490 serdes1_clk: clock@4090 {
491 compatible = "syscon";
492 reg = <0x00004090 0x4>;
493 };
494
495 serdes_mux: mux-controller {
496 compatible = "mmio-mux";
497 #mux-control-cells = <1>;
498 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
499 <0x4090 0x3>; /* SERDES1 lane select */
500 };
501
502 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]503 compatible = "ti,am654-dss-oldi-io-ctrl", "syscon";
504 reg = <0x41e0 0x14>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]505 };
506
507 ehrpwm_tbclk: clock-controller@4140 {
508 compatible = "ti,am654-ehrpwm-tbclk";
509 reg = <0x4140 0x18>;
510 #clock-cells = <1>;
511 };
512 };
513
514 dwc3_0: dwc3@4000000 {
515 compatible = "ti,am654-dwc3";
516 reg = <0x0 0x4000000 0x0 0x4000>;
517 #address-cells = <1>;
518 #size-cells = <1>;
519 ranges = <0x0 0x0 0x4000000 0x20000>;
520 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
521 dma-coherent;
522 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
523 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
524 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
525 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
526 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
527
528 usb0: usb@10000 {
529 compatible = "snps,dwc3";
530 reg = <0x10000 0x10000>;
531 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
534 interrupt-names = "peripheral",
535 "host",
536 "otg";
537 maximum-speed = "high-speed";
538 dr_mode = "otg";
539 phys = <&usb0_phy>;
540 phy-names = "usb2-phy";
541 snps,dis_u3_susphy_quirk;
542 };
543 };
544
545 usb0_phy: phy@4100000 {
546 compatible = "ti,am654-usb2", "ti,omap-usb2";
547 reg = <0x0 0x4100000 0x0 0x54>;
548 syscon-phy-power = <&scm_conf 0x4000>;
549 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
550 clock-names = "wkupclk", "refclk";
551 #phy-cells = <0>;
552 };
553
554 dwc3_1: dwc3@4020000 {
555 compatible = "ti,am654-dwc3";
556 reg = <0x0 0x4020000 0x0 0x4000>;
557 #address-cells = <1>;
558 #size-cells = <1>;
559 ranges = <0x0 0x0 0x4020000 0x20000>;
560 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
561 dma-coherent;
562 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
563 clocks = <&k3_clks 152 2>;
564 assigned-clocks = <&k3_clks 152 2>;
565 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
566
567 usb1: usb@10000 {
568 compatible = "snps,dwc3";
569 reg = <0x10000 0x10000>;
570 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "peripheral",
574 "host",
575 "otg";
576 maximum-speed = "high-speed";
577 dr_mode = "otg";
578 phys = <&usb1_phy>;
579 phy-names = "usb2-phy";
580 };
581 };
582
583 usb1_phy: phy@4110000 {
584 compatible = "ti,am654-usb2", "ti,omap-usb2";
585 reg = <0x0 0x4110000 0x0 0x54>;
586 syscon-phy-power = <&scm_conf 0x4020>;
587 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
588 clock-names = "wkupclk", "refclk";
589 #phy-cells = <0>;
590 };
591
592 intr_main_gpio: interrupt-controller@a00000 {
593 compatible = "ti,sci-intr";
594 reg = <0x0 0x00a00000 0x0 0x400>;
595 ti,intr-trigger-type = <1>;
596 interrupt-controller;
597 interrupt-parent = <&gic500>;
598 #interrupt-cells = <1>;
599 ti,sci = <&dmsc>;
600 ti,sci-dev-id = <100>;
601 ti,interrupt-ranges = <0 392 32>;
602 };
603
604 main_navss: bus@30800000 {
605 compatible = "simple-bus";
606 #address-cells = <2>;
607 #size-cells = <2>;
608 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
609 dma-coherent;
610 dma-ranges;
611
612 ti,sci-dev-id = <118>;
613
614 intr_main_navss: interrupt-controller@310e0000 {
615 compatible = "ti,sci-intr";
616 reg = <0x0 0x310e0000 0x0 0x2000>;
617 ti,intr-trigger-type = <4>;
618 interrupt-controller;
619 interrupt-parent = <&gic500>;
620 #interrupt-cells = <1>;
621 ti,sci = <&dmsc>;
622 ti,sci-dev-id = <182>;
623 ti,interrupt-ranges = <0 64 64>,
624 <64 448 64>;
625 };
626
627 inta_main_udmass: interrupt-controller@33d00000 {
628 compatible = "ti,sci-inta";
629 reg = <0x0 0x33d00000 0x0 0x100000>;
630 interrupt-controller;
631 interrupt-parent = <&intr_main_navss>;
632 msi-controller;
633 #interrupt-cells = <0>;
634 ti,sci = <&dmsc>;
635 ti,sci-dev-id = <179>;
636 ti,interrupt-ranges = <0 0 256>;
637 };
638
639 secure_proxy_main: mailbox@32c00000 {
640 compatible = "ti,am654-secure-proxy";
641 #mbox-cells = <1>;
642 reg-names = "target_data", "rt", "scfg";
643 reg = <0x00 0x32c00000 0x00 0x100000>,
644 <0x00 0x32400000 0x00 0x100000>,
645 <0x00 0x32800000 0x00 0x100000>;
646 interrupt-names = "rx_011";
647 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
648 };
649
650 hwspinlock: spinlock@30e00000 {
651 compatible = "ti,am654-hwspinlock";
652 reg = <0x00 0x30e00000 0x00 0x1000>;
653 #hwlock-cells = <1>;
654 };
655
656 mailbox0_cluster0: mailbox@31f80000 {
657 compatible = "ti,am654-mailbox";
658 reg = <0x00 0x31f80000 0x00 0x200>;
659 #mbox-cells = <1>;
660 ti,mbox-num-users = <4>;
661 ti,mbox-num-fifos = <16>;
662 interrupt-parent = <&intr_main_navss>;
663 status = "disabled";
664 };
665
666 mailbox0_cluster1: mailbox@31f81000 {
667 compatible = "ti,am654-mailbox";
668 reg = <0x00 0x31f81000 0x00 0x200>;
669 #mbox-cells = <1>;
670 ti,mbox-num-users = <4>;
671 ti,mbox-num-fifos = <16>;
672 interrupt-parent = <&intr_main_navss>;
673 status = "disabled";
674 };
675
676 mailbox0_cluster2: mailbox@31f82000 {
677 compatible = "ti,am654-mailbox";
678 reg = <0x00 0x31f82000 0x00 0x200>;
679 #mbox-cells = <1>;
680 ti,mbox-num-users = <4>;
681 ti,mbox-num-fifos = <16>;
682 interrupt-parent = <&intr_main_navss>;
683 status = "disabled";
684 };
685
686 mailbox0_cluster3: mailbox@31f83000 {
687 compatible = "ti,am654-mailbox";
688 reg = <0x00 0x31f83000 0x00 0x200>;
689 #mbox-cells = <1>;
690 ti,mbox-num-users = <4>;
691 ti,mbox-num-fifos = <16>;
692 interrupt-parent = <&intr_main_navss>;
693 status = "disabled";
694 };
695
696 mailbox0_cluster4: mailbox@31f84000 {
697 compatible = "ti,am654-mailbox";
698 reg = <0x00 0x31f84000 0x00 0x200>;
699 #mbox-cells = <1>;
700 ti,mbox-num-users = <4>;
701 ti,mbox-num-fifos = <16>;
702 interrupt-parent = <&intr_main_navss>;
703 status = "disabled";
704 };
705
706 mailbox0_cluster5: mailbox@31f85000 {
707 compatible = "ti,am654-mailbox";
708 reg = <0x00 0x31f85000 0x00 0x200>;
709 #mbox-cells = <1>;
710 ti,mbox-num-users = <4>;
711 ti,mbox-num-fifos = <16>;
712 interrupt-parent = <&intr_main_navss>;
713 status = "disabled";
714 };
715
716 mailbox0_cluster6: mailbox@31f86000 {
717 compatible = "ti,am654-mailbox";
718 reg = <0x00 0x31f86000 0x00 0x200>;
719 #mbox-cells = <1>;
720 ti,mbox-num-users = <4>;
721 ti,mbox-num-fifos = <16>;
722 interrupt-parent = <&intr_main_navss>;
723 status = "disabled";
724 };
725
726 mailbox0_cluster7: mailbox@31f87000 {
727 compatible = "ti,am654-mailbox";
728 reg = <0x00 0x31f87000 0x00 0x200>;
729 #mbox-cells = <1>;
730 ti,mbox-num-users = <4>;
731 ti,mbox-num-fifos = <16>;
732 interrupt-parent = <&intr_main_navss>;
733 status = "disabled";
734 };
735
736 mailbox0_cluster8: mailbox@31f88000 {
737 compatible = "ti,am654-mailbox";
738 reg = <0x00 0x31f88000 0x00 0x200>;
739 #mbox-cells = <1>;
740 ti,mbox-num-users = <4>;
741 ti,mbox-num-fifos = <16>;
742 interrupt-parent = <&intr_main_navss>;
743 status = "disabled";
744 };
745
746 mailbox0_cluster9: mailbox@31f89000 {
747 compatible = "ti,am654-mailbox";
748 reg = <0x00 0x31f89000 0x00 0x200>;
749 #mbox-cells = <1>;
750 ti,mbox-num-users = <4>;
751 ti,mbox-num-fifos = <16>;
752 interrupt-parent = <&intr_main_navss>;
753 status = "disabled";
754 };
755
756 mailbox0_cluster10: mailbox@31f8a000 {
757 compatible = "ti,am654-mailbox";
758 reg = <0x00 0x31f8a000 0x00 0x200>;
759 #mbox-cells = <1>;
760 ti,mbox-num-users = <4>;
761 ti,mbox-num-fifos = <16>;
762 interrupt-parent = <&intr_main_navss>;
763 status = "disabled";
764 };
765
766 mailbox0_cluster11: mailbox@31f8b000 {
767 compatible = "ti,am654-mailbox";
768 reg = <0x00 0x31f8b000 0x00 0x200>;
769 #mbox-cells = <1>;
770 ti,mbox-num-users = <4>;
771 ti,mbox-num-fifos = <16>;
772 interrupt-parent = <&intr_main_navss>;
773 status = "disabled";
774 };
775
776 ringacc: ringacc@3c000000 {
777 compatible = "ti,am654-navss-ringacc";
778 reg = <0x0 0x3c000000 0x0 0x400000>,
779 <0x0 0x38000000 0x0 0x400000>,
780 <0x0 0x31120000 0x0 0x100>,
781 <0x0 0x33000000 0x0 0x40000>,
782 <0x0 0x31080000 0x0 0x40000>;
783 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
784 ti,num-rings = <818>;
785 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
786 ti,sci = <&dmsc>;
787 ti,sci-dev-id = <187>;
788 msi-parent = <&inta_main_udmass>;
789 };
790
791 main_udmap: dma-controller@31150000 {
792 compatible = "ti,am654-navss-main-udmap";
793 reg = <0x0 0x31150000 0x0 0x100>,
794 <0x0 0x34000000 0x0 0x100000>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]795 <0x0 0x35000000 0x0 0x100000>,
796 <0x0 0x30b00000 0x0 0x10000>,
797 <0x0 0x30c00000 0x0 0x10000>,
798 <0x0 0x30d00000 0x0 0x8000>;
799 reg-names = "gcfg", "rchanrt", "tchanrt",
800 "tchan", "rchan", "rflow";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]801 msi-parent = <&inta_main_udmass>;
802 #dma-cells = <1>;
803
804 ti,sci = <&dmsc>;
805 ti,sci-dev-id = <188>;
806 ti,ringacc = <&ringacc>;
807
808 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
809 <0xd>; /* TX_CHAN */
810 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
811 <0xa>; /* RX_CHAN */
812 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
813 };
814
815 cpts@310d0000 {
816 compatible = "ti,am65-cpts";
817 reg = <0x0 0x310d0000 0x0 0x400>;
818 reg-names = "cpts";
819 clocks = <&main_cpts_mux>;
820 clock-names = "cpts";
821 interrupts-extended = <&intr_main_navss 391>;
822 interrupt-names = "cpts";
823 ti,cpts-periodic-outputs = <6>;
824 ti,cpts-ext-ts-inputs = <8>;
825
826 main_cpts_mux: refclk-mux {
827 #clock-cells = <0>;
828 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
829 <&k3_clks 118 6>, <&k3_clks 118 3>,
830 <&k3_clks 118 8>, <&k3_clks 118 14>,
831 <&k3_clks 120 3>, <&k3_clks 121 3>;
832 assigned-clocks = <&main_cpts_mux>;
833 assigned-clock-parents = <&k3_clks 118 5>;
834 };
835 };
836 };
837
838 main_gpio0: gpio@600000 {
839 compatible = "ti,am654-gpio", "ti,keystone-gpio";
840 reg = <0x0 0x600000 0x0 0x100>;
841 gpio-controller;
842 #gpio-cells = <2>;
843 interrupt-parent = <&intr_main_gpio>;
844 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
845 interrupt-controller;
846 #interrupt-cells = <2>;
847 ti,ngpio = <96>;
848 ti,davinci-gpio-unbanked = <0>;
849 clocks = <&k3_clks 57 0>;
850 clock-names = "gpio";
851 };
852
853 main_gpio1: gpio@601000 {
854 compatible = "ti,am654-gpio", "ti,keystone-gpio";
855 reg = <0x0 0x601000 0x0 0x100>;
856 gpio-controller;
857 #gpio-cells = <2>;
858 interrupt-parent = <&intr_main_gpio>;
859 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
860 interrupt-controller;
861 #interrupt-cells = <2>;
862 ti,ngpio = <90>;
863 ti,davinci-gpio-unbanked = <0>;
864 clocks = <&k3_clks 58 0>;
865 clock-names = "gpio";
866 };
867
868 pcie0_rc: pcie@5500000 {
869 compatible = "ti,am654-pcie-rc";
870 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
871 reg-names = "app", "dbics", "config", "atu";
872 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
873 #address-cells = <3>;
874 #size-cells = <2>;
875 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
876 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
877 ti,syscon-pcie-id = <&scm_conf 0x210>;
878 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
879 bus-range = <0x0 0xff>;
880 num-viewport = <16>;
881 max-link-speed = <2>;
882 dma-coherent;
883 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
884 msi-map = <0x0 &gic_its 0x0 0x10000>;
885 device_type = "pci";
886 status = "disabled";
887 };
888
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]889 pcie1_rc: pcie@5600000 {
890 compatible = "ti,am654-pcie-rc";
891 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
892 reg-names = "app", "dbics", "config", "atu";
893 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
894 #address-cells = <3>;
895 #size-cells = <2>;
896 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
897 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
898 ti,syscon-pcie-id = <&scm_conf 0x210>;
899 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
900 bus-range = <0x0 0xff>;
901 num-viewport = <16>;
902 max-link-speed = <2>;
903 dma-coherent;
904 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
905 msi-map = <0x0 &gic_its 0x10000 0x10000>;
906 device_type = "pci";
907 status = "disabled";
908 };
909
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]910 mcasp0: mcasp@2b00000 {
911 compatible = "ti,am33xx-mcasp-audio";
912 reg = <0x0 0x02b00000 0x0 0x2000>,
913 <0x0 0x02b08000 0x0 0x1000>;
914 reg-names = "mpu","dat";
915 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
917 interrupt-names = "tx", "rx";
918
919 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
920 dma-names = "tx", "rx";
921
922 clocks = <&k3_clks 104 0>;
923 clock-names = "fck";
924 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
925 status = "disabled";
926 };
927
928 mcasp1: mcasp@2b10000 {
929 compatible = "ti,am33xx-mcasp-audio";
930 reg = <0x0 0x02b10000 0x0 0x2000>,
931 <0x0 0x02b18000 0x0 0x1000>;
932 reg-names = "mpu","dat";
933 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
935 interrupt-names = "tx", "rx";
936
937 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
938 dma-names = "tx", "rx";
939
940 clocks = <&k3_clks 105 0>;
941 clock-names = "fck";
942 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
943 status = "disabled";
944 };
945
946 mcasp2: mcasp@2b20000 {
947 compatible = "ti,am33xx-mcasp-audio";
948 reg = <0x0 0x02b20000 0x0 0x2000>,
949 <0x0 0x02b28000 0x0 0x1000>;
950 reg-names = "mpu","dat";
951 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
953 interrupt-names = "tx", "rx";
954
955 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
956 dma-names = "tx", "rx";
957
958 clocks = <&k3_clks 106 0>;
959 clock-names = "fck";
960 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
961 status = "disabled";
962 };
963
964 cal: cal@6f03000 {
965 compatible = "ti,am654-cal";
966 reg = <0x0 0x06f03000 0x0 0x400>,
967 <0x0 0x06f03800 0x0 0x40>;
968 reg-names = "cal_top",
969 "cal_rx_core0";
970 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
971 ti,camerrx-control = <&scm_conf 0x40c0>;
972 clock-names = "fck";
973 clocks = <&k3_clks 2 0>;
974 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
975
976 ports {
977 #address-cells = <1>;
978 #size-cells = <0>;
979
980 csi2_0: port@0 {
981 reg = <0>;
982 };
983 };
984 };
985
986 dss: dss@4a00000 {
987 compatible = "ti,am65x-dss";
988 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
989 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
990 <0x0 0x04a06000 0x0 0x1000>, /* vid */
991 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
992 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
993 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]994 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */
995 <0x0 0x04a01000 0x0 0x1000>; /* common1 */
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]996 reg-names = "common", "vidl1", "vid",
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]997 "ovr1", "ovr2", "vp1", "vp2", "common1";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]998
999 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
1000
1001 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1002
1003 clocks = <&k3_clks 67 1>,
1004 <&k3_clks 216 1>,
1005 <&k3_clks 67 2>;
1006 clock-names = "fck", "vp1", "vp2";
1007
1008 /*
1009 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
1010 * DIV1. See "Figure 12-3365. DSS Integration"
1011 * in AM65x TRM for details.
1012 */
1013 assigned-clocks = <&k3_clks 67 2>;
1014 assigned-clock-parents = <&k3_clks 67 5>;
1015
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1016 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1017
1018 dma-coherent;
1019
1020 dss_ports: ports {
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 };
1024 };
1025
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]1026 gpu: gpu@7000000 {
1027 compatible = "ti,am6548-gpu", "img,powervr-sgx544";
1028 reg = <0x0 0x7000000 0x0 0x10000>;
1029 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1030 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1031 };
1032
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1033 ehrpwm0: pwm@3000000 {
1034 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1035 #pwm-cells = <3>;
1036 reg = <0x0 0x3000000 0x0 0x100>;
1037 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
1038 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
1039 clock-names = "tbclk", "fck";
1040 status = "disabled";
1041 };
1042
1043 ehrpwm1: pwm@3010000 {
1044 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1045 #pwm-cells = <3>;
1046 reg = <0x0 0x3010000 0x0 0x100>;
1047 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
1048 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
1049 clock-names = "tbclk", "fck";
1050 status = "disabled";
1051 };
1052
1053 ehrpwm2: pwm@3020000 {
1054 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1055 #pwm-cells = <3>;
1056 reg = <0x0 0x3020000 0x0 0x100>;
1057 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
1058 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
1059 clock-names = "tbclk", "fck";
1060 status = "disabled";
1061 };
1062
1063 ehrpwm3: pwm@3030000 {
1064 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1065 #pwm-cells = <3>;
1066 reg = <0x0 0x3030000 0x0 0x100>;
1067 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
1068 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
1069 clock-names = "tbclk", "fck";
1070 status = "disabled";
1071 };
1072
1073 ehrpwm4: pwm@3040000 {
1074 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1075 #pwm-cells = <3>;
1076 reg = <0x0 0x3040000 0x0 0x100>;
1077 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
1078 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
1079 clock-names = "tbclk", "fck";
1080 status = "disabled";
1081 };
1082
1083 ehrpwm5: pwm@3050000 {
1084 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1085 #pwm-cells = <3>;
1086 reg = <0x0 0x3050000 0x0 0x100>;
1087 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
1088 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
1089 clock-names = "tbclk", "fck";
1090 status = "disabled";
1091 };
1092
1093 icssg0: icssg@b000000 {
1094 compatible = "ti,am654-icssg";
1095 reg = <0x00 0xb000000 0x00 0x80000>;
1096 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1097 #address-cells = <1>;
1098 #size-cells = <1>;
1099 ranges = <0x0 0x00 0xb000000 0x80000>;
1100
1101 icssg0_mem: memories@0 {
1102 reg = <0x0 0x2000>,
1103 <0x2000 0x2000>,
1104 <0x10000 0x10000>;
1105 reg-names = "dram0", "dram1",
1106 "shrdram2";
1107 };
1108
1109 icssg0_cfg: cfg@26000 {
1110 compatible = "ti,pruss-cfg", "syscon";
1111 reg = <0x26000 0x200>;
1112 #address-cells = <1>;
1113 #size-cells = <1>;
1114 ranges = <0x0 0x26000 0x2000>;
1115
1116 clocks {
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119
1120 icssg0_coreclk_mux: coreclk-mux@3c {
1121 reg = <0x3c>;
1122 #clock-cells = <0>;
1123 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
1124 <&k3_clks 62 3>; /* icssg0_iclk */
1125 assigned-clocks = <&icssg0_coreclk_mux>;
1126 assigned-clock-parents = <&k3_clks 62 3>;
1127 };
1128
1129 icssg0_iepclk_mux: iepclk-mux@30 {
1130 reg = <0x30>;
1131 #clock-cells = <0>;
1132 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
1133 <&icssg0_coreclk_mux>; /* core_clk */
1134 assigned-clocks = <&icssg0_iepclk_mux>;
1135 assigned-clock-parents = <&icssg0_coreclk_mux>;
1136 };
1137 };
1138 };
1139
1140 icssg0_iep0: iep@2e000 {
1141 compatible = "ti,am654-icss-iep";
1142 reg = <0x2e000 0x1000>;
1143 clocks = <&icssg0_iepclk_mux>;
1144 };
1145
1146 icssg0_iep1: iep@2f000 {
1147 compatible = "ti,am654-icss-iep";
1148 reg = <0x2f000 0x1000>;
1149 clocks = <&icssg0_iepclk_mux>;
1150 };
1151
1152 icssg0_mii_rt: mii-rt@32000 {
1153 compatible = "ti,pruss-mii", "syscon";
1154 reg = <0x32000 0x100>;
1155 };
1156
1157 icssg0_mii_g_rt: mii-g-rt@33000 {
1158 compatible = "ti,pruss-mii-g", "syscon";
1159 reg = <0x33000 0x1000>;
1160 };
1161
1162 icssg0_intc: interrupt-controller@20000 {
1163 compatible = "ti,icssg-intc";
1164 reg = <0x20000 0x2000>;
1165 interrupt-controller;
1166 #interrupt-cells = <3>;
1167 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1175 interrupt-names = "host_intr0", "host_intr1",
1176 "host_intr2", "host_intr3",
1177 "host_intr4", "host_intr5",
1178 "host_intr6", "host_intr7";
1179 };
1180
1181 pru0_0: pru@34000 {
1182 compatible = "ti,am654-pru";
1183 reg = <0x34000 0x4000>,
1184 <0x22000 0x100>,
1185 <0x22400 0x100>;
1186 reg-names = "iram", "control", "debug";
1187 firmware-name = "am65x-pru0_0-fw";
1188 };
1189
1190 rtu0_0: rtu@4000 {
1191 compatible = "ti,am654-rtu";
1192 reg = <0x4000 0x2000>,
1193 <0x23000 0x100>,
1194 <0x23400 0x100>;
1195 reg-names = "iram", "control", "debug";
1196 firmware-name = "am65x-rtu0_0-fw";
1197 };
1198
1199 tx_pru0_0: txpru@a000 {
1200 compatible = "ti,am654-tx-pru";
1201 reg = <0xa000 0x1800>,
1202 <0x25000 0x100>,
1203 <0x25400 0x100>;
1204 reg-names = "iram", "control", "debug";
1205 firmware-name = "am65x-txpru0_0-fw";
1206 };
1207
1208 pru0_1: pru@38000 {
1209 compatible = "ti,am654-pru";
1210 reg = <0x38000 0x4000>,
1211 <0x24000 0x100>,
1212 <0x24400 0x100>;
1213 reg-names = "iram", "control", "debug";
1214 firmware-name = "am65x-pru0_1-fw";
1215 };
1216
1217 rtu0_1: rtu@6000 {
1218 compatible = "ti,am654-rtu";
1219 reg = <0x6000 0x2000>,
1220 <0x23800 0x100>,
1221 <0x23c00 0x100>;
1222 reg-names = "iram", "control", "debug";
1223 firmware-name = "am65x-rtu0_1-fw";
1224 };
1225
1226 tx_pru0_1: txpru@c000 {
1227 compatible = "ti,am654-tx-pru";
1228 reg = <0xc000 0x1800>,
1229 <0x25800 0x100>,
1230 <0x25c00 0x100>;
1231 reg-names = "iram", "control", "debug";
1232 firmware-name = "am65x-txpru0_1-fw";
1233 };
1234
1235 icssg0_mdio: mdio@32400 {
1236 compatible = "ti,davinci_mdio";
1237 reg = <0x32400 0x100>;
1238 clocks = <&k3_clks 62 3>;
1239 clock-names = "fck";
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1242 bus_freq = <1000000>;
1243 status = "disabled";
1244 };
1245 };
1246
1247 icssg1: icssg@b100000 {
1248 compatible = "ti,am654-icssg";
1249 reg = <0x00 0xb100000 0x00 0x80000>;
1250 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1251 #address-cells = <1>;
1252 #size-cells = <1>;
1253 ranges = <0x0 0x00 0xb100000 0x80000>;
1254
1255 icssg1_mem: memories@0 {
1256 reg = <0x0 0x2000>,
1257 <0x2000 0x2000>,
1258 <0x10000 0x10000>;
1259 reg-names = "dram0", "dram1",
1260 "shrdram2";
1261 };
1262
1263 icssg1_cfg: cfg@26000 {
1264 compatible = "ti,pruss-cfg", "syscon";
1265 reg = <0x26000 0x200>;
1266 #address-cells = <1>;
1267 #size-cells = <1>;
1268 ranges = <0x0 0x26000 0x2000>;
1269
1270 clocks {
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1273
1274 icssg1_coreclk_mux: coreclk-mux@3c {
1275 reg = <0x3c>;
1276 #clock-cells = <0>;
1277 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
1278 <&k3_clks 63 3>; /* icssg1_iclk */
1279 assigned-clocks = <&icssg1_coreclk_mux>;
1280 assigned-clock-parents = <&k3_clks 63 3>;
1281 };
1282
1283 icssg1_iepclk_mux: iepclk-mux@30 {
1284 reg = <0x30>;
1285 #clock-cells = <0>;
1286 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
1287 <&icssg1_coreclk_mux>; /* core_clk */
1288 assigned-clocks = <&icssg1_iepclk_mux>;
1289 assigned-clock-parents = <&icssg1_coreclk_mux>;
1290 };
1291 };
1292 };
1293
1294 icssg1_iep0: iep@2e000 {
1295 compatible = "ti,am654-icss-iep";
1296 reg = <0x2e000 0x1000>;
1297 clocks = <&icssg1_iepclk_mux>;
1298 };
1299
1300 icssg1_iep1: iep@2f000 {
1301 compatible = "ti,am654-icss-iep";
1302 reg = <0x2f000 0x1000>;
1303 clocks = <&icssg1_iepclk_mux>;
1304 };
1305
1306 icssg1_mii_rt: mii-rt@32000 {
1307 compatible = "ti,pruss-mii", "syscon";
1308 reg = <0x32000 0x100>;
1309 };
1310
1311 icssg1_mii_g_rt: mii-g-rt@33000 {
1312 compatible = "ti,pruss-mii-g", "syscon";
1313 reg = <0x33000 0x1000>;
1314 };
1315
1316 icssg1_intc: interrupt-controller@20000 {
1317 compatible = "ti,icssg-intc";
1318 reg = <0x20000 0x2000>;
1319 interrupt-controller;
1320 #interrupt-cells = <3>;
1321 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1329 interrupt-names = "host_intr0", "host_intr1",
1330 "host_intr2", "host_intr3",
1331 "host_intr4", "host_intr5",
1332 "host_intr6", "host_intr7";
1333 };
1334
1335 pru1_0: pru@34000 {
1336 compatible = "ti,am654-pru";
1337 reg = <0x34000 0x4000>,
1338 <0x22000 0x100>,
1339 <0x22400 0x100>;
1340 reg-names = "iram", "control", "debug";
1341 firmware-name = "am65x-pru1_0-fw";
1342 };
1343
1344 rtu1_0: rtu@4000 {
1345 compatible = "ti,am654-rtu";
1346 reg = <0x4000 0x2000>,
1347 <0x23000 0x100>,
1348 <0x23400 0x100>;
1349 reg-names = "iram", "control", "debug";
1350 firmware-name = "am65x-rtu1_0-fw";
1351 };
1352
1353 tx_pru1_0: txpru@a000 {
1354 compatible = "ti,am654-tx-pru";
1355 reg = <0xa000 0x1800>,
1356 <0x25000 0x100>,
1357 <0x25400 0x100>;
1358 reg-names = "iram", "control", "debug";
1359 firmware-name = "am65x-txpru1_0-fw";
1360 };
1361
1362 pru1_1: pru@38000 {
1363 compatible = "ti,am654-pru";
1364 reg = <0x38000 0x4000>,
1365 <0x24000 0x100>,
1366 <0x24400 0x100>;
1367 reg-names = "iram", "control", "debug";
1368 firmware-name = "am65x-pru1_1-fw";
1369 };
1370
1371 rtu1_1: rtu@6000 {
1372 compatible = "ti,am654-rtu";
1373 reg = <0x6000 0x2000>,
1374 <0x23800 0x100>,
1375 <0x23c00 0x100>;
1376 reg-names = "iram", "control", "debug";
1377 firmware-name = "am65x-rtu1_1-fw";
1378 };
1379
1380 tx_pru1_1: txpru@c000 {
1381 compatible = "ti,am654-tx-pru";
1382 reg = <0xc000 0x1800>,
1383 <0x25800 0x100>,
1384 <0x25c00 0x100>;
1385 reg-names = "iram", "control", "debug";
1386 firmware-name = "am65x-txpru1_1-fw";
1387 };
1388
1389 icssg1_mdio: mdio@32400 {
1390 compatible = "ti,davinci_mdio";
1391 reg = <0x32400 0x100>;
1392 clocks = <&k3_clks 63 3>;
1393 clock-names = "fck";
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1396 bus_freq = <1000000>;
1397 status = "disabled";
1398 };
1399 };
1400
1401 icssg2: icssg@b200000 {
1402 compatible = "ti,am654-icssg";
1403 reg = <0x00 0xb200000 0x00 0x80000>;
1404 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1405 #address-cells = <1>;
1406 #size-cells = <1>;
1407 ranges = <0x0 0x00 0xb200000 0x80000>;
1408
1409 icssg2_mem: memories@0 {
1410 reg = <0x0 0x2000>,
1411 <0x2000 0x2000>,
1412 <0x10000 0x10000>;
1413 reg-names = "dram0", "dram1",
1414 "shrdram2";
1415 };
1416
1417 icssg2_cfg: cfg@26000 {
1418 compatible = "ti,pruss-cfg", "syscon";
1419 reg = <0x26000 0x200>;
1420 #address-cells = <1>;
1421 #size-cells = <1>;
1422 ranges = <0x0 0x26000 0x2000>;
1423
1424 clocks {
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1427
1428 icssg2_coreclk_mux: coreclk-mux@3c {
1429 reg = <0x3c>;
1430 #clock-cells = <0>;
1431 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
1432 <&k3_clks 64 3>; /* icssg1_iclk */
1433 assigned-clocks = <&icssg2_coreclk_mux>;
1434 assigned-clock-parents = <&k3_clks 64 3>;
1435 };
1436
1437 icssg2_iepclk_mux: iepclk-mux@30 {
1438 reg = <0x30>;
1439 #clock-cells = <0>;
1440 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
1441 <&icssg2_coreclk_mux>; /* core_clk */
1442 assigned-clocks = <&icssg2_iepclk_mux>;
1443 assigned-clock-parents = <&icssg2_coreclk_mux>;
1444 };
1445 };
1446 };
1447
1448 icssg2_iep0: iep@2e000 {
1449 compatible = "ti,am654-icss-iep";
1450 reg = <0x2e000 0x1000>;
1451 clocks = <&icssg2_iepclk_mux>;
1452 };
1453
1454 icssg2_iep1: iep@2f000 {
1455 compatible = "ti,am654-icss-iep";
1456 reg = <0x2f000 0x1000>;
1457 clocks = <&icssg2_iepclk_mux>;
1458 };
1459
1460 icssg2_mii_rt: mii-rt@32000 {
1461 compatible = "ti,pruss-mii", "syscon";
1462 reg = <0x32000 0x100>;
1463 };
1464
1465 icssg2_mii_g_rt: mii-g-rt@33000 {
1466 compatible = "ti,pruss-mii-g", "syscon";
1467 reg = <0x33000 0x1000>;
1468 };
1469
1470 icssg2_intc: interrupt-controller@20000 {
1471 compatible = "ti,icssg-intc";
1472 reg = <0x20000 0x2000>;
1473 interrupt-controller;
1474 #interrupt-cells = <3>;
1475 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
1483 interrupt-names = "host_intr0", "host_intr1",
1484 "host_intr2", "host_intr3",
1485 "host_intr4", "host_intr5",
1486 "host_intr6", "host_intr7";
1487 };
1488
1489 pru2_0: pru@34000 {
1490 compatible = "ti,am654-pru";
1491 reg = <0x34000 0x4000>,
1492 <0x22000 0x100>,
1493 <0x22400 0x100>;
1494 reg-names = "iram", "control", "debug";
1495 firmware-name = "am65x-pru2_0-fw";
1496 };
1497
1498 rtu2_0: rtu@4000 {
1499 compatible = "ti,am654-rtu";
1500 reg = <0x4000 0x2000>,
1501 <0x23000 0x100>,
1502 <0x23400 0x100>;
1503 reg-names = "iram", "control", "debug";
1504 firmware-name = "am65x-rtu2_0-fw";
1505 };
1506
1507 tx_pru2_0: txpru@a000 {
1508 compatible = "ti,am654-tx-pru";
1509 reg = <0xa000 0x1800>,
1510 <0x25000 0x100>,
1511 <0x25400 0x100>;
1512 reg-names = "iram", "control", "debug";
1513 firmware-name = "am65x-txpru2_0-fw";
1514 };
1515
1516 pru2_1: pru@38000 {
1517 compatible = "ti,am654-pru";
1518 reg = <0x38000 0x4000>,
1519 <0x24000 0x100>,
1520 <0x24400 0x100>;
1521 reg-names = "iram", "control", "debug";
1522 firmware-name = "am65x-pru2_1-fw";
1523 };
1524
1525 rtu2_1: rtu@6000 {
1526 compatible = "ti,am654-rtu";
1527 reg = <0x6000 0x2000>,
1528 <0x23800 0x100>,
1529 <0x23c00 0x100>;
1530 reg-names = "iram", "control", "debug";
1531 firmware-name = "am65x-rtu2_1-fw";
1532 };
1533
1534 tx_pru2_1: txpru@c000 {
1535 compatible = "ti,am654-tx-pru";
1536 reg = <0xc000 0x1800>,
1537 <0x25800 0x100>,
1538 <0x25c00 0x100>;
1539 reg-names = "iram", "control", "debug";
1540 firmware-name = "am65x-txpru2_1-fw";
1541 };
1542
1543 icssg2_mdio: mdio@32400 {
1544 compatible = "ti,davinci_mdio";
1545 reg = <0x32400 0x100>;
1546 clocks = <&k3_clks 64 3>;
1547 clock-names = "fck";
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1550 bus_freq = <1000000>;
1551 status = "disabled";
1552 };
1553 };
1554};