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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm64 / rockchip / rk3588s.dtsi
blob: 87b83c87bd55155623342fe002ad67cbe104b83c [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rk3588-cru.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/power/rk3588-power.h>
10#include <dt-bindings/reset/rockchip,rk3588-cru.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/ata/ahci.h>
13
14/ {
15 compatible = "rockchip,rk3588";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]21 aliases {
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 i2c5 = &i2c5;
33 i2c6 = &i2c6;
34 i2c7 = &i2c7;
35 i2c8 = &i2c8;
36 serial0 = &uart0;
37 serial1 = &uart1;
38 serial2 = &uart2;
39 serial3 = &uart3;
40 serial4 = &uart4;
41 serial5 = &uart5;
42 serial6 = &uart6;
43 serial7 = &uart7;
44 serial8 = &uart8;
45 serial9 = &uart9;
46 spi0 = &spi0;
47 spi1 = &spi1;
48 spi2 = &spi2;
49 spi3 = &spi3;
50 spi4 = &spi4;
51 };
52
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 cpu-map {
58 cluster0 {
59 core0 {
60 cpu = <&cpu_l0>;
61 };
62 core1 {
63 cpu = <&cpu_l1>;
64 };
65 core2 {
66 cpu = <&cpu_l2>;
67 };
68 core3 {
69 cpu = <&cpu_l3>;
70 };
71 };
72 cluster1 {
73 core0 {
74 cpu = <&cpu_b0>;
75 };
76 core1 {
77 cpu = <&cpu_b1>;
78 };
79 };
80 cluster2 {
81 core0 {
82 cpu = <&cpu_b2>;
83 };
84 core1 {
85 cpu = <&cpu_b3>;
86 };
87 };
88 };
89
90 cpu_l0: cpu@0 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a55";
93 reg = <0x0>;
94 enable-method = "psci";
95 capacity-dmips-mhz = <530>;
96 clocks = <&scmi_clk SCMI_CLK_CPUL>;
97 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
98 assigned-clock-rates = <816000000>;
99 cpu-idle-states = <&CPU_SLEEP>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_cache_l0>;
107 dynamic-power-coefficient = <228>;
108 #cooling-cells = <2>;
109 };
110
111 cpu_l1: cpu@100 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a55";
114 reg = <0x100>;
115 enable-method = "psci";
116 capacity-dmips-mhz = <530>;
117 clocks = <&scmi_clk SCMI_CLK_CPUL>;
118 cpu-idle-states = <&CPU_SLEEP>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_cache_l1>;
126 dynamic-power-coefficient = <228>;
127 #cooling-cells = <2>;
128 };
129
130 cpu_l2: cpu@200 {
131 device_type = "cpu";
132 compatible = "arm,cortex-a55";
133 reg = <0x200>;
134 enable-method = "psci";
135 capacity-dmips-mhz = <530>;
136 clocks = <&scmi_clk SCMI_CLK_CPUL>;
137 cpu-idle-states = <&CPU_SLEEP>;
138 i-cache-size = <32768>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <128>;
141 d-cache-size = <32768>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <128>;
144 next-level-cache = <&l2_cache_l2>;
145 dynamic-power-coefficient = <228>;
146 #cooling-cells = <2>;
147 };
148
149 cpu_l3: cpu@300 {
150 device_type = "cpu";
151 compatible = "arm,cortex-a55";
152 reg = <0x300>;
153 enable-method = "psci";
154 capacity-dmips-mhz = <530>;
155 clocks = <&scmi_clk SCMI_CLK_CPUL>;
156 cpu-idle-states = <&CPU_SLEEP>;
157 i-cache-size = <32768>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <128>;
160 d-cache-size = <32768>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <128>;
163 next-level-cache = <&l2_cache_l3>;
164 dynamic-power-coefficient = <228>;
165 #cooling-cells = <2>;
166 };
167
168 cpu_b0: cpu@400 {
169 device_type = "cpu";
170 compatible = "arm,cortex-a76";
171 reg = <0x400>;
172 enable-method = "psci";
173 capacity-dmips-mhz = <1024>;
174 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
175 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
176 assigned-clock-rates = <816000000>;
177 cpu-idle-states = <&CPU_SLEEP>;
178 i-cache-size = <65536>;
179 i-cache-line-size = <64>;
180 i-cache-sets = <256>;
181 d-cache-size = <65536>;
182 d-cache-line-size = <64>;
183 d-cache-sets = <256>;
184 next-level-cache = <&l2_cache_b0>;
185 dynamic-power-coefficient = <416>;
186 #cooling-cells = <2>;
187 };
188
189 cpu_b1: cpu@500 {
190 device_type = "cpu";
191 compatible = "arm,cortex-a76";
192 reg = <0x500>;
193 enable-method = "psci";
194 capacity-dmips-mhz = <1024>;
195 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
196 cpu-idle-states = <&CPU_SLEEP>;
197 i-cache-size = <65536>;
198 i-cache-line-size = <64>;
199 i-cache-sets = <256>;
200 d-cache-size = <65536>;
201 d-cache-line-size = <64>;
202 d-cache-sets = <256>;
203 next-level-cache = <&l2_cache_b1>;
204 dynamic-power-coefficient = <416>;
205 #cooling-cells = <2>;
206 };
207
208 cpu_b2: cpu@600 {
209 device_type = "cpu";
210 compatible = "arm,cortex-a76";
211 reg = <0x600>;
212 enable-method = "psci";
213 capacity-dmips-mhz = <1024>;
214 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
215 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
216 assigned-clock-rates = <816000000>;
217 cpu-idle-states = <&CPU_SLEEP>;
218 i-cache-size = <65536>;
219 i-cache-line-size = <64>;
220 i-cache-sets = <256>;
221 d-cache-size = <65536>;
222 d-cache-line-size = <64>;
223 d-cache-sets = <256>;
224 next-level-cache = <&l2_cache_b2>;
225 dynamic-power-coefficient = <416>;
226 #cooling-cells = <2>;
227 };
228
229 cpu_b3: cpu@700 {
230 device_type = "cpu";
231 compatible = "arm,cortex-a76";
232 reg = <0x700>;
233 enable-method = "psci";
234 capacity-dmips-mhz = <1024>;
235 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
236 cpu-idle-states = <&CPU_SLEEP>;
237 i-cache-size = <65536>;
238 i-cache-line-size = <64>;
239 i-cache-sets = <256>;
240 d-cache-size = <65536>;
241 d-cache-line-size = <64>;
242 d-cache-sets = <256>;
243 next-level-cache = <&l2_cache_b3>;
244 dynamic-power-coefficient = <416>;
245 #cooling-cells = <2>;
246 };
247
248 idle-states {
249 entry-method = "psci";
250 CPU_SLEEP: cpu-sleep {
251 compatible = "arm,idle-state";
252 local-timer-stop;
253 arm,psci-suspend-param = <0x0010000>;
254 entry-latency-us = <100>;
255 exit-latency-us = <120>;
256 min-residency-us = <1000>;
257 };
258 };
259
260 l2_cache_l0: l2-cache-l0 {
261 compatible = "cache";
262 cache-size = <131072>;
263 cache-line-size = <64>;
264 cache-sets = <512>;
265 cache-level = <2>;
266 cache-unified;
267 next-level-cache = <&l3_cache>;
268 };
269
270 l2_cache_l1: l2-cache-l1 {
271 compatible = "cache";
272 cache-size = <131072>;
273 cache-line-size = <64>;
274 cache-sets = <512>;
275 cache-level = <2>;
276 cache-unified;
277 next-level-cache = <&l3_cache>;
278 };
279
280 l2_cache_l2: l2-cache-l2 {
281 compatible = "cache";
282 cache-size = <131072>;
283 cache-line-size = <64>;
284 cache-sets = <512>;
285 cache-level = <2>;
286 cache-unified;
287 next-level-cache = <&l3_cache>;
288 };
289
290 l2_cache_l3: l2-cache-l3 {
291 compatible = "cache";
292 cache-size = <131072>;
293 cache-line-size = <64>;
294 cache-sets = <512>;
295 cache-level = <2>;
296 cache-unified;
297 next-level-cache = <&l3_cache>;
298 };
299
300 l2_cache_b0: l2-cache-b0 {
301 compatible = "cache";
302 cache-size = <524288>;
303 cache-line-size = <64>;
304 cache-sets = <1024>;
305 cache-level = <2>;
306 cache-unified;
307 next-level-cache = <&l3_cache>;
308 };
309
310 l2_cache_b1: l2-cache-b1 {
311 compatible = "cache";
312 cache-size = <524288>;
313 cache-line-size = <64>;
314 cache-sets = <1024>;
315 cache-level = <2>;
316 cache-unified;
317 next-level-cache = <&l3_cache>;
318 };
319
320 l2_cache_b2: l2-cache-b2 {
321 compatible = "cache";
322 cache-size = <524288>;
323 cache-line-size = <64>;
324 cache-sets = <1024>;
325 cache-level = <2>;
326 cache-unified;
327 next-level-cache = <&l3_cache>;
328 };
329
330 l2_cache_b3: l2-cache-b3 {
331 compatible = "cache";
332 cache-size = <524288>;
333 cache-line-size = <64>;
334 cache-sets = <1024>;
335 cache-level = <2>;
336 cache-unified;
337 next-level-cache = <&l3_cache>;
338 };
339
340 l3_cache: l3-cache {
341 compatible = "cache";
342 cache-size = <3145728>;
343 cache-line-size = <64>;
344 cache-sets = <4096>;
345 cache-level = <3>;
346 cache-unified;
347 };
348 };
349
350 firmware {
351 optee: optee {
352 compatible = "linaro,optee-tz";
353 method = "smc";
354 };
355
356 scmi: scmi {
357 compatible = "arm,scmi-smc";
358 arm,smc-id = <0x82000010>;
359 shmem = <&scmi_shmem>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362
363 scmi_clk: protocol@14 {
364 reg = <0x14>;
365 #clock-cells = <1>;
366 };
367
368 scmi_reset: protocol@16 {
369 reg = <0x16>;
370 #reset-cells = <1>;
371 };
372 };
373 };
374
375 pmu-a55 {
376 compatible = "arm,cortex-a55-pmu";
377 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
378 };
379
380 pmu-a76 {
381 compatible = "arm,cortex-a76-pmu";
382 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
383 };
384
385 psci {
386 compatible = "arm,psci-1.0";
387 method = "smc";
388 };
389
390 spll: clock-0 {
391 compatible = "fixed-clock";
392 clock-frequency = <702000000>;
393 clock-output-names = "spll";
394 #clock-cells = <0>;
395 };
396
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]397 display_subsystem: display-subsystem {
398 compatible = "rockchip,display-subsystem";
399 ports = <&vop_out>;
400 };
401
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]402 timer {
403 compatible = "arm,armv8-timer";
404 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
405 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
406 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
407 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
408 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
409 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
410 };
411
412 xin24m: clock-1 {
413 compatible = "fixed-clock";
414 clock-frequency = <24000000>;
415 clock-output-names = "xin24m";
416 #clock-cells = <0>;
417 };
418
419 xin32k: clock-2 {
420 compatible = "fixed-clock";
421 clock-frequency = <32768>;
422 clock-output-names = "xin32k";
423 #clock-cells = <0>;
424 };
425
426 pmu_sram: sram@10f000 {
427 compatible = "mmio-sram";
428 reg = <0x0 0x0010f000 0x0 0x100>;
429 ranges = <0 0x0 0x0010f000 0x100>;
430 #address-cells = <1>;
431 #size-cells = <1>;
432
433 scmi_shmem: sram@0 {
434 compatible = "arm,scmi-shmem";
435 reg = <0x0 0x100>;
436 };
437 };
438
439 usb_host0_ehci: usb@fc800000 {
440 compatible = "rockchip,rk3588-ehci", "generic-ehci";
441 reg = <0x0 0xfc800000 0x0 0x40000>;
442 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
443 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
444 phys = <&u2phy2_host>;
445 phy-names = "usb";
446 power-domains = <&power RK3588_PD_USB>;
447 status = "disabled";
448 };
449
450 usb_host0_ohci: usb@fc840000 {
451 compatible = "rockchip,rk3588-ohci", "generic-ohci";
452 reg = <0x0 0xfc840000 0x0 0x40000>;
453 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
454 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
455 phys = <&u2phy2_host>;
456 phy-names = "usb";
457 power-domains = <&power RK3588_PD_USB>;
458 status = "disabled";
459 };
460
461 usb_host1_ehci: usb@fc880000 {
462 compatible = "rockchip,rk3588-ehci", "generic-ehci";
463 reg = <0x0 0xfc880000 0x0 0x40000>;
464 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
465 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
466 phys = <&u2phy3_host>;
467 phy-names = "usb";
468 power-domains = <&power RK3588_PD_USB>;
469 status = "disabled";
470 };
471
472 usb_host1_ohci: usb@fc8c0000 {
473 compatible = "rockchip,rk3588-ohci", "generic-ohci";
474 reg = <0x0 0xfc8c0000 0x0 0x40000>;
475 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
476 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
477 phys = <&u2phy3_host>;
478 phy-names = "usb";
479 power-domains = <&power RK3588_PD_USB>;
480 status = "disabled";
481 };
482
483 usb_host2_xhci: usb@fcd00000 {
484 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
485 reg = <0x0 0xfcd00000 0x0 0x400000>;
486 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
487 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
488 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
489 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
490 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
491 dr_mode = "host";
492 phys = <&combphy2_psu PHY_TYPE_USB3>;
493 phy-names = "usb3-phy";
494 phy_type = "utmi_wide";
495 resets = <&cru SRST_A_USB3OTG2>;
496 snps,dis_enblslpm_quirk;
497 snps,dis-u2-freeclk-exists-quirk;
498 snps,dis-del-phy-power-chg-quirk;
499 snps,dis-tx-ipgap-linecheck-quirk;
500 snps,dis_rxdet_inp3_quirk;
501 status = "disabled";
502 };
503
504 pmu1grf: syscon@fd58a000 {
505 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
506 reg = <0x0 0xfd58a000 0x0 0x10000>;
507 };
508
509 sys_grf: syscon@fd58c000 {
510 compatible = "rockchip,rk3588-sys-grf", "syscon";
511 reg = <0x0 0xfd58c000 0x0 0x1000>;
512 };
513
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]514 vop_grf: syscon@fd5a4000 {
515 compatible = "rockchip,rk3588-vop-grf", "syscon";
516 reg = <0x0 0xfd5a4000 0x0 0x2000>;
517 };
518
519 vo1_grf: syscon@fd5a8000 {
520 compatible = "rockchip,rk3588-vo-grf", "syscon";
521 reg = <0x0 0xfd5a8000 0x0 0x100>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]522 clocks = <&cru PCLK_VO1GRF>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]523 };
524
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]525 php_grf: syscon@fd5b0000 {
526 compatible = "rockchip,rk3588-php-grf", "syscon";
527 reg = <0x0 0xfd5b0000 0x0 0x1000>;
528 };
529
530 pipe_phy0_grf: syscon@fd5bc000 {
531 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
532 reg = <0x0 0xfd5bc000 0x0 0x100>;
533 };
534
535 pipe_phy2_grf: syscon@fd5c4000 {
536 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
537 reg = <0x0 0xfd5c4000 0x0 0x100>;
538 };
539
540 usb2phy2_grf: syscon@fd5d8000 {
541 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
542 reg = <0x0 0xfd5d8000 0x0 0x4000>;
543 #address-cells = <1>;
544 #size-cells = <1>;
545
546 u2phy2: usb2-phy@8000 {
547 compatible = "rockchip,rk3588-usb2phy";
548 reg = <0x8000 0x10>;
549 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
550 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
551 reset-names = "phy", "apb";
552 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
553 clock-names = "phyclk";
554 clock-output-names = "usb480m_phy2";
555 #clock-cells = <0>;
556 status = "disabled";
557
558 u2phy2_host: host-port {
559 #phy-cells = <0>;
560 status = "disabled";
561 };
562 };
563 };
564
565 usb2phy3_grf: syscon@fd5dc000 {
566 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
567 reg = <0x0 0xfd5dc000 0x0 0x4000>;
568 #address-cells = <1>;
569 #size-cells = <1>;
570
571 u2phy3: usb2-phy@c000 {
572 compatible = "rockchip,rk3588-usb2phy";
573 reg = <0xc000 0x10>;
574 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
575 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
576 reset-names = "phy", "apb";
577 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
578 clock-names = "phyclk";
579 clock-output-names = "usb480m_phy3";
580 #clock-cells = <0>;
581 status = "disabled";
582
583 u2phy3_host: host-port {
584 #phy-cells = <0>;
585 status = "disabled";
586 };
587 };
588 };
589
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]590 hdptxphy0_grf: syscon@fd5e0000 {
591 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
592 reg = <0x0 0xfd5e0000 0x0 0x100>;
593 };
594
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]595 ioc: syscon@fd5f0000 {
596 compatible = "rockchip,rk3588-ioc", "syscon";
597 reg = <0x0 0xfd5f0000 0x0 0x10000>;
598 };
599
600 system_sram1: sram@fd600000 {
601 compatible = "mmio-sram";
602 reg = <0x0 0xfd600000 0x0 0x100000>;
603 ranges = <0x0 0x0 0xfd600000 0x100000>;
604 #address-cells = <1>;
605 #size-cells = <1>;
606 };
607
608 cru: clock-controller@fd7c0000 {
609 compatible = "rockchip,rk3588-cru";
610 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
611 assigned-clocks =
612 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
613 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
614 <&cru ACLK_CENTER_ROOT>,
615 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
616 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
617 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
618 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
619 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
620 <&cru CLK_GPU>;
621 assigned-clock-rates =
622 <1100000000>, <786432000>,
623 <850000000>, <1188000000>,
624 <702000000>,
625 <400000000>, <500000000>,
626 <800000000>, <100000000>,
627 <400000000>, <100000000>,
628 <200000000>, <500000000>,
629 <375000000>, <150000000>,
630 <200000000>;
631 rockchip,grf = <&php_grf>;
632 #clock-cells = <1>;
633 #reset-cells = <1>;
634 };
635
636 i2c0: i2c@fd880000 {
637 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
638 reg = <0x0 0xfd880000 0x0 0x1000>;
639 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
640 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
641 clock-names = "i2c", "pclk";
642 pinctrl-0 = <&i2c0m0_xfer>;
643 pinctrl-names = "default";
644 #address-cells = <1>;
645 #size-cells = <0>;
646 status = "disabled";
647 };
648
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]649 vop: vop@fdd90000 {
650 compatible = "rockchip,rk3588-vop";
651 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
652 reg-names = "vop", "gamma-lut";
653 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
654 clocks = <&cru ACLK_VOP>,
655 <&cru HCLK_VOP>,
656 <&cru DCLK_VOP0>,
657 <&cru DCLK_VOP1>,
658 <&cru DCLK_VOP2>,
659 <&cru DCLK_VOP3>,
660 <&cru PCLK_VOP_ROOT>;
661 clock-names = "aclk",
662 "hclk",
663 "dclk_vp0",
664 "dclk_vp1",
665 "dclk_vp2",
666 "dclk_vp3",
667 "pclk_vop";
668 iommus = <&vop_mmu>;
669 power-domains = <&power RK3588_PD_VOP>;
670 rockchip,grf = <&sys_grf>;
671 rockchip,vop-grf = <&vop_grf>;
672 rockchip,vo1-grf = <&vo1_grf>;
673 rockchip,pmu = <&pmu>;
674 status = "disabled";
675
676 vop_out: ports {
677 #address-cells = <1>;
678 #size-cells = <0>;
679
680 vp0: port@0 {
681 #address-cells = <1>;
682 #size-cells = <0>;
683 reg = <0>;
684 };
685
686 vp1: port@1 {
687 #address-cells = <1>;
688 #size-cells = <0>;
689 reg = <1>;
690 };
691
692 vp2: port@2 {
693 #address-cells = <1>;
694 #size-cells = <0>;
695 reg = <2>;
696 };
697
698 vp3: port@3 {
699 #address-cells = <1>;
700 #size-cells = <0>;
701 reg = <3>;
702 };
703 };
704 };
705
706 vop_mmu: iommu@fdd97e00 {
707 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
708 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
709 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
710 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
711 clock-names = "aclk", "iface";
712 #iommu-cells = <0>;
713 power-domains = <&power RK3588_PD_VOP>;
714 status = "disabled";
715 };
716
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]717 uart0: serial@fd890000 {
718 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
719 reg = <0x0 0xfd890000 0x0 0x100>;
720 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
721 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
722 clock-names = "baudclk", "apb_pclk";
723 dmas = <&dmac0 6>, <&dmac0 7>;
724 dma-names = "tx", "rx";
725 pinctrl-0 = <&uart0m1_xfer>;
726 pinctrl-names = "default";
727 reg-shift = <2>;
728 reg-io-width = <4>;
729 status = "disabled";
730 };
731
732 pwm0: pwm@fd8b0000 {
733 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
734 reg = <0x0 0xfd8b0000 0x0 0x10>;
735 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
736 clock-names = "pwm", "pclk";
737 pinctrl-0 = <&pwm0m0_pins>;
738 pinctrl-names = "default";
739 #pwm-cells = <3>;
740 status = "disabled";
741 };
742
743 pwm1: pwm@fd8b0010 {
744 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
745 reg = <0x0 0xfd8b0010 0x0 0x10>;
746 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
747 clock-names = "pwm", "pclk";
748 pinctrl-0 = <&pwm1m0_pins>;
749 pinctrl-names = "default";
750 #pwm-cells = <3>;
751 status = "disabled";
752 };
753
754 pwm2: pwm@fd8b0020 {
755 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
756 reg = <0x0 0xfd8b0020 0x0 0x10>;
757 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
758 clock-names = "pwm", "pclk";
759 pinctrl-0 = <&pwm2m0_pins>;
760 pinctrl-names = "default";
761 #pwm-cells = <3>;
762 status = "disabled";
763 };
764
765 pwm3: pwm@fd8b0030 {
766 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
767 reg = <0x0 0xfd8b0030 0x0 0x10>;
768 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
769 clock-names = "pwm", "pclk";
770 pinctrl-0 = <&pwm3m0_pins>;
771 pinctrl-names = "default";
772 #pwm-cells = <3>;
773 status = "disabled";
774 };
775
776 pmu: power-management@fd8d8000 {
777 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
778 reg = <0x0 0xfd8d8000 0x0 0x400>;
779
780 power: power-controller {
781 compatible = "rockchip,rk3588-power-controller";
782 #address-cells = <1>;
783 #power-domain-cells = <1>;
784 #size-cells = <0>;
785 status = "okay";
786
787 /* These power domains are grouped by VD_NPU */
788 power-domain@RK3588_PD_NPU {
789 reg = <RK3588_PD_NPU>;
790 #power-domain-cells = <0>;
791 #address-cells = <1>;
792 #size-cells = <0>;
793
794 power-domain@RK3588_PD_NPUTOP {
795 reg = <RK3588_PD_NPUTOP>;
796 clocks = <&cru HCLK_NPU_ROOT>,
797 <&cru PCLK_NPU_ROOT>,
798 <&cru CLK_NPU_DSU0>,
799 <&cru HCLK_NPU_CM0_ROOT>;
800 pm_qos = <&qos_npu0_mwr>,
801 <&qos_npu0_mro>,
802 <&qos_mcu_npu>;
803 #power-domain-cells = <0>;
804 #address-cells = <1>;
805 #size-cells = <0>;
806
807 power-domain@RK3588_PD_NPU1 {
808 reg = <RK3588_PD_NPU1>;
809 clocks = <&cru HCLK_NPU_ROOT>,
810 <&cru PCLK_NPU_ROOT>,
811 <&cru CLK_NPU_DSU0>;
812 pm_qos = <&qos_npu1>;
813 #power-domain-cells = <0>;
814 };
815 power-domain@RK3588_PD_NPU2 {
816 reg = <RK3588_PD_NPU2>;
817 clocks = <&cru HCLK_NPU_ROOT>,
818 <&cru PCLK_NPU_ROOT>,
819 <&cru CLK_NPU_DSU0>;
820 pm_qos = <&qos_npu2>;
821 #power-domain-cells = <0>;
822 };
823 };
824 };
825 /* These power domains are grouped by VD_GPU */
826 power-domain@RK3588_PD_GPU {
827 reg = <RK3588_PD_GPU>;
828 clocks = <&cru CLK_GPU>,
829 <&cru CLK_GPU_COREGROUP>,
830 <&cru CLK_GPU_STACKS>;
831 pm_qos = <&qos_gpu_m0>,
832 <&qos_gpu_m1>,
833 <&qos_gpu_m2>,
834 <&qos_gpu_m3>;
835 #power-domain-cells = <0>;
836 };
837 /* These power domains are grouped by VD_VCODEC */
838 power-domain@RK3588_PD_VCODEC {
839 reg = <RK3588_PD_VCODEC>;
840 #address-cells = <1>;
841 #size-cells = <0>;
842 #power-domain-cells = <0>;
843
844 power-domain@RK3588_PD_RKVDEC0 {
845 reg = <RK3588_PD_RKVDEC0>;
846 clocks = <&cru HCLK_RKVDEC0>,
847 <&cru HCLK_VDPU_ROOT>,
848 <&cru ACLK_VDPU_ROOT>,
849 <&cru ACLK_RKVDEC0>,
850 <&cru ACLK_RKVDEC_CCU>;
851 pm_qos = <&qos_rkvdec0>;
852 #power-domain-cells = <0>;
853 };
854 power-domain@RK3588_PD_RKVDEC1 {
855 reg = <RK3588_PD_RKVDEC1>;
856 clocks = <&cru HCLK_RKVDEC1>,
857 <&cru HCLK_VDPU_ROOT>,
858 <&cru ACLK_VDPU_ROOT>,
859 <&cru ACLK_RKVDEC1>;
860 pm_qos = <&qos_rkvdec1>;
861 #power-domain-cells = <0>;
862 };
863 power-domain@RK3588_PD_VENC0 {
864 reg = <RK3588_PD_VENC0>;
865 clocks = <&cru HCLK_RKVENC0>,
866 <&cru ACLK_RKVENC0>;
867 pm_qos = <&qos_rkvenc0_m0ro>,
868 <&qos_rkvenc0_m1ro>,
869 <&qos_rkvenc0_m2wo>;
870 #address-cells = <1>;
871 #size-cells = <0>;
872 #power-domain-cells = <0>;
873
874 power-domain@RK3588_PD_VENC1 {
875 reg = <RK3588_PD_VENC1>;
876 clocks = <&cru HCLK_RKVENC1>,
877 <&cru HCLK_RKVENC0>,
878 <&cru ACLK_RKVENC0>,
879 <&cru ACLK_RKVENC1>;
880 pm_qos = <&qos_rkvenc1_m0ro>,
881 <&qos_rkvenc1_m1ro>,
882 <&qos_rkvenc1_m2wo>;
883 #power-domain-cells = <0>;
884 };
885 };
886 };
887 /* These power domains are grouped by VD_LOGIC */
888 power-domain@RK3588_PD_VDPU {
889 reg = <RK3588_PD_VDPU>;
890 clocks = <&cru HCLK_VDPU_ROOT>,
891 <&cru ACLK_VDPU_LOW_ROOT>,
892 <&cru ACLK_VDPU_ROOT>,
893 <&cru ACLK_JPEG_DECODER_ROOT>,
894 <&cru ACLK_IEP2P0>,
895 <&cru HCLK_IEP2P0>,
896 <&cru ACLK_JPEG_ENCODER0>,
897 <&cru HCLK_JPEG_ENCODER0>,
898 <&cru ACLK_JPEG_ENCODER1>,
899 <&cru HCLK_JPEG_ENCODER1>,
900 <&cru ACLK_JPEG_ENCODER2>,
901 <&cru HCLK_JPEG_ENCODER2>,
902 <&cru ACLK_JPEG_ENCODER3>,
903 <&cru HCLK_JPEG_ENCODER3>,
904 <&cru ACLK_JPEG_DECODER>,
905 <&cru HCLK_JPEG_DECODER>,
906 <&cru ACLK_RGA2>,
907 <&cru HCLK_RGA2>;
908 pm_qos = <&qos_iep>,
909 <&qos_jpeg_dec>,
910 <&qos_jpeg_enc0>,
911 <&qos_jpeg_enc1>,
912 <&qos_jpeg_enc2>,
913 <&qos_jpeg_enc3>,
914 <&qos_rga2_mro>,
915 <&qos_rga2_mwo>;
916 #address-cells = <1>;
917 #size-cells = <0>;
918 #power-domain-cells = <0>;
919
920
921 power-domain@RK3588_PD_AV1 {
922 reg = <RK3588_PD_AV1>;
923 clocks = <&cru PCLK_AV1>,
924 <&cru ACLK_AV1>,
925 <&cru HCLK_VDPU_ROOT>;
926 pm_qos = <&qos_av1>;
927 #power-domain-cells = <0>;
928 };
929 power-domain@RK3588_PD_RKVDEC0 {
930 reg = <RK3588_PD_RKVDEC0>;
931 clocks = <&cru HCLK_RKVDEC0>,
932 <&cru HCLK_VDPU_ROOT>,
933 <&cru ACLK_VDPU_ROOT>,
934 <&cru ACLK_RKVDEC0>;
935 pm_qos = <&qos_rkvdec0>;
936 #power-domain-cells = <0>;
937 };
938 power-domain@RK3588_PD_RKVDEC1 {
939 reg = <RK3588_PD_RKVDEC1>;
940 clocks = <&cru HCLK_RKVDEC1>,
941 <&cru HCLK_VDPU_ROOT>,
942 <&cru ACLK_VDPU_ROOT>;
943 pm_qos = <&qos_rkvdec1>;
944 #power-domain-cells = <0>;
945 };
946 power-domain@RK3588_PD_RGA30 {
947 reg = <RK3588_PD_RGA30>;
948 clocks = <&cru ACLK_RGA3_0>,
949 <&cru HCLK_RGA3_0>;
950 pm_qos = <&qos_rga3_0>;
951 #power-domain-cells = <0>;
952 };
953 };
954 power-domain@RK3588_PD_VOP {
955 reg = <RK3588_PD_VOP>;
956 clocks = <&cru PCLK_VOP_ROOT>,
957 <&cru HCLK_VOP_ROOT>,
958 <&cru ACLK_VOP>;
959 pm_qos = <&qos_vop_m0>,
960 <&qos_vop_m1>;
961 #address-cells = <1>;
962 #size-cells = <0>;
963 #power-domain-cells = <0>;
964
965 power-domain@RK3588_PD_VO0 {
966 reg = <RK3588_PD_VO0>;
967 clocks = <&cru PCLK_VO0_ROOT>,
968 <&cru PCLK_VO0_S_ROOT>,
969 <&cru HCLK_VO0_S_ROOT>,
970 <&cru ACLK_VO0_ROOT>,
971 <&cru HCLK_HDCP0>,
972 <&cru ACLK_HDCP0>,
973 <&cru HCLK_VOP_ROOT>;
974 pm_qos = <&qos_hdcp0>;
975 #power-domain-cells = <0>;
976 };
977 };
978 power-domain@RK3588_PD_VO1 {
979 reg = <RK3588_PD_VO1>;
980 clocks = <&cru PCLK_VO1_ROOT>,
981 <&cru PCLK_VO1_S_ROOT>,
982 <&cru HCLK_VO1_S_ROOT>,
983 <&cru HCLK_HDCP1>,
984 <&cru ACLK_HDCP1>,
985 <&cru ACLK_HDMIRX_ROOT>,
986 <&cru HCLK_VO1USB_TOP_ROOT>;
987 pm_qos = <&qos_hdcp1>,
988 <&qos_hdmirx>;
989 #power-domain-cells = <0>;
990 };
991 power-domain@RK3588_PD_VI {
992 reg = <RK3588_PD_VI>;
993 clocks = <&cru HCLK_VI_ROOT>,
994 <&cru PCLK_VI_ROOT>,
995 <&cru HCLK_ISP0>,
996 <&cru ACLK_ISP0>,
997 <&cru HCLK_VICAP>,
998 <&cru ACLK_VICAP>;
999 pm_qos = <&qos_isp0_mro>,
1000 <&qos_isp0_mwo>,
1001 <&qos_vicap_m0>,
1002 <&qos_vicap_m1>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 #power-domain-cells = <0>;
1006
1007 power-domain@RK3588_PD_ISP1 {
1008 reg = <RK3588_PD_ISP1>;
1009 clocks = <&cru HCLK_ISP1>,
1010 <&cru ACLK_ISP1>,
1011 <&cru HCLK_VI_ROOT>,
1012 <&cru PCLK_VI_ROOT>;
1013 pm_qos = <&qos_isp1_mwo>,
1014 <&qos_isp1_mro>;
1015 #power-domain-cells = <0>;
1016 };
1017 power-domain@RK3588_PD_FEC {
1018 reg = <RK3588_PD_FEC>;
1019 clocks = <&cru HCLK_FISHEYE0>,
1020 <&cru ACLK_FISHEYE0>,
1021 <&cru HCLK_FISHEYE1>,
1022 <&cru ACLK_FISHEYE1>,
1023 <&cru PCLK_VI_ROOT>;
1024 pm_qos = <&qos_fisheye0>,
1025 <&qos_fisheye1>;
1026 #power-domain-cells = <0>;
1027 };
1028 };
1029 power-domain@RK3588_PD_RGA31 {
1030 reg = <RK3588_PD_RGA31>;
1031 clocks = <&cru HCLK_RGA3_1>,
1032 <&cru ACLK_RGA3_1>;
1033 pm_qos = <&qos_rga3_1>;
1034 #power-domain-cells = <0>;
1035 };
1036 power-domain@RK3588_PD_USB {
1037 reg = <RK3588_PD_USB>;
1038 clocks = <&cru PCLK_PHP_ROOT>,
1039 <&cru ACLK_USB_ROOT>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1040 <&cru ACLK_USB>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1041 <&cru HCLK_USB_ROOT>,
1042 <&cru HCLK_HOST0>,
1043 <&cru HCLK_HOST_ARB0>,
1044 <&cru HCLK_HOST1>,
1045 <&cru HCLK_HOST_ARB1>;
1046 pm_qos = <&qos_usb3_0>,
1047 <&qos_usb3_1>,
1048 <&qos_usb2host_0>,
1049 <&qos_usb2host_1>;
1050 #power-domain-cells = <0>;
1051 };
1052 power-domain@RK3588_PD_GMAC {
1053 reg = <RK3588_PD_GMAC>;
1054 clocks = <&cru PCLK_PHP_ROOT>,
1055 <&cru ACLK_PCIE_ROOT>,
1056 <&cru ACLK_PHP_ROOT>;
1057 #power-domain-cells = <0>;
1058 };
1059 power-domain@RK3588_PD_PCIE {
1060 reg = <RK3588_PD_PCIE>;
1061 clocks = <&cru PCLK_PHP_ROOT>,
1062 <&cru ACLK_PCIE_ROOT>,
1063 <&cru ACLK_PHP_ROOT>;
1064 #power-domain-cells = <0>;
1065 };
1066 power-domain@RK3588_PD_SDIO {
1067 reg = <RK3588_PD_SDIO>;
1068 clocks = <&cru HCLK_SDIO>,
1069 <&cru HCLK_NVM_ROOT>;
1070 pm_qos = <&qos_sdio>;
1071 #power-domain-cells = <0>;
1072 };
1073 power-domain@RK3588_PD_AUDIO {
1074 reg = <RK3588_PD_AUDIO>;
1075 clocks = <&cru HCLK_AUDIO_ROOT>,
1076 <&cru PCLK_AUDIO_ROOT>;
1077 #power-domain-cells = <0>;
1078 };
1079 power-domain@RK3588_PD_SDMMC {
1080 reg = <RK3588_PD_SDMMC>;
1081 pm_qos = <&qos_sdmmc>;
1082 #power-domain-cells = <0>;
1083 };
1084 };
1085 };
1086
1087 i2s4_8ch: i2s@fddc0000 {
1088 compatible = "rockchip,rk3588-i2s-tdm";
1089 reg = <0x0 0xfddc0000 0x0 0x1000>;
1090 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
1091 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
1092 clock-names = "mclk_tx", "mclk_rx", "hclk";
1093 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1094 assigned-clock-parents = <&cru PLL_AUPLL>;
1095 dmas = <&dmac2 0>;
1096 dma-names = "tx";
1097 power-domains = <&power RK3588_PD_VO0>;
1098 resets = <&cru SRST_M_I2S4_8CH_TX>;
1099 reset-names = "tx-m";
1100 #sound-dai-cells = <0>;
1101 status = "disabled";
1102 };
1103
1104 i2s5_8ch: i2s@fddf0000 {
1105 compatible = "rockchip,rk3588-i2s-tdm";
1106 reg = <0x0 0xfddf0000 0x0 0x1000>;
1107 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
1108 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
1109 clock-names = "mclk_tx", "mclk_rx", "hclk";
1110 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1111 assigned-clock-parents = <&cru PLL_AUPLL>;
1112 dmas = <&dmac2 2>;
1113 dma-names = "tx";
1114 power-domains = <&power RK3588_PD_VO1>;
1115 resets = <&cru SRST_M_I2S5_8CH_TX>;
1116 reset-names = "tx-m";
1117 #sound-dai-cells = <0>;
1118 status = "disabled";
1119 };
1120
1121 i2s9_8ch: i2s@fddfc000 {
1122 compatible = "rockchip,rk3588-i2s-tdm";
1123 reg = <0x0 0xfddfc000 0x0 0x1000>;
1124 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
1125 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
1126 clock-names = "mclk_tx", "mclk_rx", "hclk";
1127 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1128 assigned-clock-parents = <&cru PLL_AUPLL>;
1129 dmas = <&dmac2 23>;
1130 dma-names = "rx";
1131 power-domains = <&power RK3588_PD_VO1>;
1132 resets = <&cru SRST_M_I2S9_8CH_RX>;
1133 reset-names = "rx-m";
1134 #sound-dai-cells = <0>;
1135 status = "disabled";
1136 };
1137
1138 qos_gpu_m0: qos@fdf35000 {
1139 compatible = "rockchip,rk3588-qos", "syscon";
1140 reg = <0x0 0xfdf35000 0x0 0x20>;
1141 };
1142
1143 qos_gpu_m1: qos@fdf35200 {
1144 compatible = "rockchip,rk3588-qos", "syscon";
1145 reg = <0x0 0xfdf35200 0x0 0x20>;
1146 };
1147
1148 qos_gpu_m2: qos@fdf35400 {
1149 compatible = "rockchip,rk3588-qos", "syscon";
1150 reg = <0x0 0xfdf35400 0x0 0x20>;
1151 };
1152
1153 qos_gpu_m3: qos@fdf35600 {
1154 compatible = "rockchip,rk3588-qos", "syscon";
1155 reg = <0x0 0xfdf35600 0x0 0x20>;
1156 };
1157
1158 qos_rga3_1: qos@fdf36000 {
1159 compatible = "rockchip,rk3588-qos", "syscon";
1160 reg = <0x0 0xfdf36000 0x0 0x20>;
1161 };
1162
1163 qos_sdio: qos@fdf39000 {
1164 compatible = "rockchip,rk3588-qos", "syscon";
1165 reg = <0x0 0xfdf39000 0x0 0x20>;
1166 };
1167
1168 qos_sdmmc: qos@fdf3d800 {
1169 compatible = "rockchip,rk3588-qos", "syscon";
1170 reg = <0x0 0xfdf3d800 0x0 0x20>;
1171 };
1172
1173 qos_usb3_1: qos@fdf3e000 {
1174 compatible = "rockchip,rk3588-qos", "syscon";
1175 reg = <0x0 0xfdf3e000 0x0 0x20>;
1176 };
1177
1178 qos_usb3_0: qos@fdf3e200 {
1179 compatible = "rockchip,rk3588-qos", "syscon";
1180 reg = <0x0 0xfdf3e200 0x0 0x20>;
1181 };
1182
1183 qos_usb2host_0: qos@fdf3e400 {
1184 compatible = "rockchip,rk3588-qos", "syscon";
1185 reg = <0x0 0xfdf3e400 0x0 0x20>;
1186 };
1187
1188 qos_usb2host_1: qos@fdf3e600 {
1189 compatible = "rockchip,rk3588-qos", "syscon";
1190 reg = <0x0 0xfdf3e600 0x0 0x20>;
1191 };
1192
1193 qos_fisheye0: qos@fdf40000 {
1194 compatible = "rockchip,rk3588-qos", "syscon";
1195 reg = <0x0 0xfdf40000 0x0 0x20>;
1196 };
1197
1198 qos_fisheye1: qos@fdf40200 {
1199 compatible = "rockchip,rk3588-qos", "syscon";
1200 reg = <0x0 0xfdf40200 0x0 0x20>;
1201 };
1202
1203 qos_isp0_mro: qos@fdf40400 {
1204 compatible = "rockchip,rk3588-qos", "syscon";
1205 reg = <0x0 0xfdf40400 0x0 0x20>;
1206 };
1207
1208 qos_isp0_mwo: qos@fdf40500 {
1209 compatible = "rockchip,rk3588-qos", "syscon";
1210 reg = <0x0 0xfdf40500 0x0 0x20>;
1211 };
1212
1213 qos_vicap_m0: qos@fdf40600 {
1214 compatible = "rockchip,rk3588-qos", "syscon";
1215 reg = <0x0 0xfdf40600 0x0 0x20>;
1216 };
1217
1218 qos_vicap_m1: qos@fdf40800 {
1219 compatible = "rockchip,rk3588-qos", "syscon";
1220 reg = <0x0 0xfdf40800 0x0 0x20>;
1221 };
1222
1223 qos_isp1_mwo: qos@fdf41000 {
1224 compatible = "rockchip,rk3588-qos", "syscon";
1225 reg = <0x0 0xfdf41000 0x0 0x20>;
1226 };
1227
1228 qos_isp1_mro: qos@fdf41100 {
1229 compatible = "rockchip,rk3588-qos", "syscon";
1230 reg = <0x0 0xfdf41100 0x0 0x20>;
1231 };
1232
1233 qos_rkvenc0_m0ro: qos@fdf60000 {
1234 compatible = "rockchip,rk3588-qos", "syscon";
1235 reg = <0x0 0xfdf60000 0x0 0x20>;
1236 };
1237
1238 qos_rkvenc0_m1ro: qos@fdf60200 {
1239 compatible = "rockchip,rk3588-qos", "syscon";
1240 reg = <0x0 0xfdf60200 0x0 0x20>;
1241 };
1242
1243 qos_rkvenc0_m2wo: qos@fdf60400 {
1244 compatible = "rockchip,rk3588-qos", "syscon";
1245 reg = <0x0 0xfdf60400 0x0 0x20>;
1246 };
1247
1248 qos_rkvenc1_m0ro: qos@fdf61000 {
1249 compatible = "rockchip,rk3588-qos", "syscon";
1250 reg = <0x0 0xfdf61000 0x0 0x20>;
1251 };
1252
1253 qos_rkvenc1_m1ro: qos@fdf61200 {
1254 compatible = "rockchip,rk3588-qos", "syscon";
1255 reg = <0x0 0xfdf61200 0x0 0x20>;
1256 };
1257
1258 qos_rkvenc1_m2wo: qos@fdf61400 {
1259 compatible = "rockchip,rk3588-qos", "syscon";
1260 reg = <0x0 0xfdf61400 0x0 0x20>;
1261 };
1262
1263 qos_rkvdec0: qos@fdf62000 {
1264 compatible = "rockchip,rk3588-qos", "syscon";
1265 reg = <0x0 0xfdf62000 0x0 0x20>;
1266 };
1267
1268 qos_rkvdec1: qos@fdf63000 {
1269 compatible = "rockchip,rk3588-qos", "syscon";
1270 reg = <0x0 0xfdf63000 0x0 0x20>;
1271 };
1272
1273 qos_av1: qos@fdf64000 {
1274 compatible = "rockchip,rk3588-qos", "syscon";
1275 reg = <0x0 0xfdf64000 0x0 0x20>;
1276 };
1277
1278 qos_iep: qos@fdf66000 {
1279 compatible = "rockchip,rk3588-qos", "syscon";
1280 reg = <0x0 0xfdf66000 0x0 0x20>;
1281 };
1282
1283 qos_jpeg_dec: qos@fdf66200 {
1284 compatible = "rockchip,rk3588-qos", "syscon";
1285 reg = <0x0 0xfdf66200 0x0 0x20>;
1286 };
1287
1288 qos_jpeg_enc0: qos@fdf66400 {
1289 compatible = "rockchip,rk3588-qos", "syscon";
1290 reg = <0x0 0xfdf66400 0x0 0x20>;
1291 };
1292
1293 qos_jpeg_enc1: qos@fdf66600 {
1294 compatible = "rockchip,rk3588-qos", "syscon";
1295 reg = <0x0 0xfdf66600 0x0 0x20>;
1296 };
1297
1298 qos_jpeg_enc2: qos@fdf66800 {
1299 compatible = "rockchip,rk3588-qos", "syscon";
1300 reg = <0x0 0xfdf66800 0x0 0x20>;
1301 };
1302
1303 qos_jpeg_enc3: qos@fdf66a00 {
1304 compatible = "rockchip,rk3588-qos", "syscon";
1305 reg = <0x0 0xfdf66a00 0x0 0x20>;
1306 };
1307
1308 qos_rga2_mro: qos@fdf66c00 {
1309 compatible = "rockchip,rk3588-qos", "syscon";
1310 reg = <0x0 0xfdf66c00 0x0 0x20>;
1311 };
1312
1313 qos_rga2_mwo: qos@fdf66e00 {
1314 compatible = "rockchip,rk3588-qos", "syscon";
1315 reg = <0x0 0xfdf66e00 0x0 0x20>;
1316 };
1317
1318 qos_rga3_0: qos@fdf67000 {
1319 compatible = "rockchip,rk3588-qos", "syscon";
1320 reg = <0x0 0xfdf67000 0x0 0x20>;
1321 };
1322
1323 qos_vdpu: qos@fdf67200 {
1324 compatible = "rockchip,rk3588-qos", "syscon";
1325 reg = <0x0 0xfdf67200 0x0 0x20>;
1326 };
1327
1328 qos_npu1: qos@fdf70000 {
1329 compatible = "rockchip,rk3588-qos", "syscon";
1330 reg = <0x0 0xfdf70000 0x0 0x20>;
1331 };
1332
1333 qos_npu2: qos@fdf71000 {
1334 compatible = "rockchip,rk3588-qos", "syscon";
1335 reg = <0x0 0xfdf71000 0x0 0x20>;
1336 };
1337
1338 qos_npu0_mwr: qos@fdf72000 {
1339 compatible = "rockchip,rk3588-qos", "syscon";
1340 reg = <0x0 0xfdf72000 0x0 0x20>;
1341 };
1342
1343 qos_npu0_mro: qos@fdf72200 {
1344 compatible = "rockchip,rk3588-qos", "syscon";
1345 reg = <0x0 0xfdf72200 0x0 0x20>;
1346 };
1347
1348 qos_mcu_npu: qos@fdf72400 {
1349 compatible = "rockchip,rk3588-qos", "syscon";
1350 reg = <0x0 0xfdf72400 0x0 0x20>;
1351 };
1352
1353 qos_hdcp0: qos@fdf80000 {
1354 compatible = "rockchip,rk3588-qos", "syscon";
1355 reg = <0x0 0xfdf80000 0x0 0x20>;
1356 };
1357
1358 qos_hdcp1: qos@fdf81000 {
1359 compatible = "rockchip,rk3588-qos", "syscon";
1360 reg = <0x0 0xfdf81000 0x0 0x20>;
1361 };
1362
1363 qos_hdmirx: qos@fdf81200 {
1364 compatible = "rockchip,rk3588-qos", "syscon";
1365 reg = <0x0 0xfdf81200 0x0 0x20>;
1366 };
1367
1368 qos_vop_m0: qos@fdf82000 {
1369 compatible = "rockchip,rk3588-qos", "syscon";
1370 reg = <0x0 0xfdf82000 0x0 0x20>;
1371 };
1372
1373 qos_vop_m1: qos@fdf82200 {
1374 compatible = "rockchip,rk3588-qos", "syscon";
1375 reg = <0x0 0xfdf82200 0x0 0x20>;
1376 };
1377
1378 pcie2x1l1: pcie@fe180000 {
1379 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1380 bus-range = <0x30 0x3f>;
1381 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1382 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1383 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1384 clock-names = "aclk_mst", "aclk_slv",
1385 "aclk_dbi", "pclk",
1386 "aux", "pipe";
1387 device_type = "pci";
1388 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1389 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1390 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1391 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1392 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1393 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1394 #interrupt-cells = <1>;
1395 interrupt-map-mask = <0 0 0 7>;
1396 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1397 <0 0 0 2 &pcie2x1l1_intc 1>,
1398 <0 0 0 3 &pcie2x1l1_intc 2>,
1399 <0 0 0 4 &pcie2x1l1_intc 3>;
1400 linux,pci-domain = <3>;
1401 max-link-speed = <2>;
1402 msi-map = <0x3000 &its0 0x3000 0x1000>;
1403 num-lanes = <1>;
1404 phys = <&combphy2_psu PHY_TYPE_PCIE>;
1405 phy-names = "pcie-phy";
1406 power-domains = <&power RK3588_PD_PCIE>;
1407 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1408 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1409 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1410 reg = <0xa 0x40c00000 0x0 0x00400000>,
1411 <0x0 0xfe180000 0x0 0x00010000>,
1412 <0x0 0xf3000000 0x0 0x00100000>;
1413 reg-names = "dbi", "apb", "config";
1414 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1415 reset-names = "pwr", "pipe";
1416 #address-cells = <3>;
1417 #size-cells = <2>;
1418 status = "disabled";
1419
1420 pcie2x1l1_intc: legacy-interrupt-controller {
1421 interrupt-controller;
1422 #address-cells = <0>;
1423 #interrupt-cells = <1>;
1424 interrupt-parent = <&gic>;
1425 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1426 };
1427 };
1428
1429 pcie2x1l2: pcie@fe190000 {
1430 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1431 bus-range = <0x40 0x4f>;
1432 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1433 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1434 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1435 clock-names = "aclk_mst", "aclk_slv",
1436 "aclk_dbi", "pclk",
1437 "aux", "pipe";
1438 device_type = "pci";
1439 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1440 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1441 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1442 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1443 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1444 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1445 #interrupt-cells = <1>;
1446 interrupt-map-mask = <0 0 0 7>;
1447 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1448 <0 0 0 2 &pcie2x1l2_intc 1>,
1449 <0 0 0 3 &pcie2x1l2_intc 2>,
1450 <0 0 0 4 &pcie2x1l2_intc 3>;
1451 linux,pci-domain = <4>;
1452 max-link-speed = <2>;
1453 msi-map = <0x4000 &its0 0x4000 0x1000>;
1454 num-lanes = <1>;
1455 phys = <&combphy0_ps PHY_TYPE_PCIE>;
1456 phy-names = "pcie-phy";
1457 power-domains = <&power RK3588_PD_PCIE>;
1458 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1459 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1460 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1461 reg = <0xa 0x41000000 0x0 0x00400000>,
1462 <0x0 0xfe190000 0x0 0x00010000>,
1463 <0x0 0xf4000000 0x0 0x00100000>;
1464 reg-names = "dbi", "apb", "config";
1465 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1466 reset-names = "pwr", "pipe";
1467 #address-cells = <3>;
1468 #size-cells = <2>;
1469 status = "disabled";
1470
1471 pcie2x1l2_intc: legacy-interrupt-controller {
1472 interrupt-controller;
1473 #address-cells = <0>;
1474 #interrupt-cells = <1>;
1475 interrupt-parent = <&gic>;
1476 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1477 };
1478 };
1479
1480 dfi: dfi@fe060000 {
1481 reg = <0x00 0xfe060000 0x00 0x10000>;
1482 compatible = "rockchip,rk3588-dfi";
1483 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
1484 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
1485 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
1486 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1487 rockchip,pmu = <&pmu1grf>;
1488 };
1489
1490 gmac1: ethernet@fe1c0000 {
1491 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1492 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1493 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1494 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1495 interrupt-names = "macirq", "eth_wake_irq";
1496 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1497 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1498 <&cru CLK_GMAC1_PTP_REF>;
1499 clock-names = "stmmaceth", "clk_mac_ref",
1500 "pclk_mac", "aclk_mac",
1501 "ptp_ref";
1502 power-domains = <&power RK3588_PD_GMAC>;
1503 resets = <&cru SRST_A_GMAC1>;
1504 reset-names = "stmmaceth";
1505 rockchip,grf = <&sys_grf>;
1506 rockchip,php-grf = <&php_grf>;
1507 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1508 snps,mixed-burst;
1509 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1510 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1511 snps,tso;
1512 status = "disabled";
1513
1514 mdio1: mdio {
1515 compatible = "snps,dwmac-mdio";
1516 #address-cells = <0x1>;
1517 #size-cells = <0x0>;
1518 };
1519
1520 gmac1_stmmac_axi_setup: stmmac-axi-config {
1521 snps,blen = <0 0 0 0 16 8 4>;
1522 snps,wr_osr_lmt = <4>;
1523 snps,rd_osr_lmt = <8>;
1524 };
1525
1526 gmac1_mtl_rx_setup: rx-queues-config {
1527 snps,rx-queues-to-use = <2>;
1528 queue0 {};
1529 queue1 {};
1530 };
1531
1532 gmac1_mtl_tx_setup: tx-queues-config {
1533 snps,tx-queues-to-use = <2>;
1534 queue0 {};
1535 queue1 {};
1536 };
1537 };
1538
1539 sata0: sata@fe210000 {
1540 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1541 reg = <0 0xfe210000 0 0x1000>;
1542 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1543 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1544 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1545 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1546 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1547 ports-implemented = <0x1>;
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1550 status = "disabled";
1551
1552 sata-port@0 {
1553 reg = <0>;
1554 hba-port-cap = <HBA_PORT_FBSCP>;
1555 phys = <&combphy0_ps PHY_TYPE_SATA>;
1556 phy-names = "sata-phy";
1557 snps,rx-ts-max = <32>;
1558 snps,tx-ts-max = <32>;
1559 };
1560 };
1561
1562 sata2: sata@fe230000 {
1563 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1564 reg = <0 0xfe230000 0 0x1000>;
1565 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1566 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1567 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1568 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1569 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1570 ports-implemented = <0x1>;
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1573 status = "disabled";
1574
1575 sata-port@0 {
1576 reg = <0>;
1577 hba-port-cap = <HBA_PORT_FBSCP>;
1578 phys = <&combphy2_psu PHY_TYPE_SATA>;
1579 phy-names = "sata-phy";
1580 snps,rx-ts-max = <32>;
1581 snps,tx-ts-max = <32>;
1582 };
1583 };
1584
1585 sfc: spi@fe2b0000 {
1586 compatible = "rockchip,sfc";
1587 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1588 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
1589 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1590 clock-names = "clk_sfc", "hclk_sfc";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1593 status = "disabled";
1594 };
1595
1596 sdmmc: mmc@fe2c0000 {
1597 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1598 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1599 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1600 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
1601 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1602 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1603 fifo-depth = <0x100>;
1604 max-frequency = <200000000>;
1605 pinctrl-names = "default";
1606 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1607 power-domains = <&power RK3588_PD_SDMMC>;
1608 status = "disabled";
1609 };
1610
1611 sdio: mmc@fe2d0000 {
1612 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1613 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1614 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1615 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1616 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1617 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1618 fifo-depth = <0x100>;
1619 max-frequency = <200000000>;
1620 pinctrl-names = "default";
1621 pinctrl-0 = <&sdiom1_pins>;
1622 power-domains = <&power RK3588_PD_SDIO>;
1623 status = "disabled";
1624 };
1625
1626 sdhci: mmc@fe2e0000 {
1627 compatible = "rockchip,rk3588-dwcmshc";
1628 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1629 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1630 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1631 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1632 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1633 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1634 <&cru TMCLK_EMMC>;
1635 clock-names = "core", "bus", "axi", "block", "timer";
1636 max-frequency = <200000000>;
1637 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1638 <&emmc_cmd>, <&emmc_data_strobe>;
1639 pinctrl-names = "default";
1640 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1641 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1642 <&cru SRST_T_EMMC>;
1643 reset-names = "core", "bus", "axi", "block", "timer";
1644 status = "disabled";
1645 };
1646
1647 i2s0_8ch: i2s@fe470000 {
1648 compatible = "rockchip,rk3588-i2s-tdm";
1649 reg = <0x0 0xfe470000 0x0 0x1000>;
1650 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1651 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1652 clock-names = "mclk_tx", "mclk_rx", "hclk";
1653 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1654 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1655 dmas = <&dmac0 0>, <&dmac0 1>;
1656 dma-names = "tx", "rx";
1657 power-domains = <&power RK3588_PD_AUDIO>;
1658 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1659 reset-names = "tx-m", "rx-m";
1660 rockchip,trcm-sync-tx-only;
1661 pinctrl-names = "default";
1662 pinctrl-0 = <&i2s0_lrck
1663 &i2s0_sclk
1664 &i2s0_sdi0
1665 &i2s0_sdi1
1666 &i2s0_sdi2
1667 &i2s0_sdi3
1668 &i2s0_sdo0
1669 &i2s0_sdo1
1670 &i2s0_sdo2
1671 &i2s0_sdo3>;
1672 #sound-dai-cells = <0>;
1673 status = "disabled";
1674 };
1675
1676 i2s1_8ch: i2s@fe480000 {
1677 compatible = "rockchip,rk3588-i2s-tdm";
1678 reg = <0x0 0xfe480000 0x0 0x1000>;
1679 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1680 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1681 clock-names = "mclk_tx", "mclk_rx", "hclk";
1682 dmas = <&dmac0 2>, <&dmac0 3>;
1683 dma-names = "tx", "rx";
1684 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1685 reset-names = "tx-m", "rx-m";
1686 rockchip,trcm-sync-tx-only;
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&i2s1m0_lrck
1689 &i2s1m0_sclk
1690 &i2s1m0_sdi0
1691 &i2s1m0_sdi1
1692 &i2s1m0_sdi2
1693 &i2s1m0_sdi3
1694 &i2s1m0_sdo0
1695 &i2s1m0_sdo1
1696 &i2s1m0_sdo2
1697 &i2s1m0_sdo3>;
1698 #sound-dai-cells = <0>;
1699 status = "disabled";
1700 };
1701
1702 i2s2_2ch: i2s@fe490000 {
1703 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1704 reg = <0x0 0xfe490000 0x0 0x1000>;
1705 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1706 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1707 clock-names = "i2s_clk", "i2s_hclk";
1708 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1709 assigned-clock-parents = <&cru PLL_AUPLL>;
1710 dmas = <&dmac1 0>, <&dmac1 1>;
1711 dma-names = "tx", "rx";
1712 power-domains = <&power RK3588_PD_AUDIO>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1713 pinctrl-names = "default";
1714 pinctrl-0 = <&i2s2m1_lrck
1715 &i2s2m1_sclk
1716 &i2s2m1_sdi
1717 &i2s2m1_sdo>;
1718 #sound-dai-cells = <0>;
1719 status = "disabled";
1720 };
1721
1722 i2s3_2ch: i2s@fe4a0000 {
1723 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1724 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1725 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
1726 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1727 clock-names = "i2s_clk", "i2s_hclk";
1728 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1729 assigned-clock-parents = <&cru PLL_AUPLL>;
1730 dmas = <&dmac1 2>, <&dmac1 3>;
1731 dma-names = "tx", "rx";
1732 power-domains = <&power RK3588_PD_AUDIO>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1733 pinctrl-names = "default";
1734 pinctrl-0 = <&i2s3_lrck
1735 &i2s3_sclk
1736 &i2s3_sdi
1737 &i2s3_sdo>;
1738 #sound-dai-cells = <0>;
1739 status = "disabled";
1740 };
1741
1742 gic: interrupt-controller@fe600000 {
1743 compatible = "arm,gic-v3";
1744 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1745 <0x0 0xfe680000 0 0x100000>; /* GICR */
1746 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1747 interrupt-controller;
1748 mbi-alias = <0x0 0xfe610000>;
1749 mbi-ranges = <424 56>;
1750 msi-controller;
1751 ranges;
1752 #address-cells = <2>;
1753 #interrupt-cells = <4>;
1754 #size-cells = <2>;
1755
1756 its0: msi-controller@fe640000 {
1757 compatible = "arm,gic-v3-its";
1758 reg = <0x0 0xfe640000 0x0 0x20000>;
1759 msi-controller;
1760 #msi-cells = <1>;
1761 };
1762
1763 its1: msi-controller@fe660000 {
1764 compatible = "arm,gic-v3-its";
1765 reg = <0x0 0xfe660000 0x0 0x20000>;
1766 msi-controller;
1767 #msi-cells = <1>;
1768 };
1769
1770 ppi-partitions {
1771 ppi_partition0: interrupt-partition-0 {
1772 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
1773 };
1774
1775 ppi_partition1: interrupt-partition-1 {
1776 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
1777 };
1778 };
1779 };
1780
1781 dmac0: dma-controller@fea10000 {
1782 compatible = "arm,pl330", "arm,primecell";
1783 reg = <0x0 0xfea10000 0x0 0x4000>;
1784 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
1785 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
1786 arm,pl330-periph-burst;
1787 clocks = <&cru ACLK_DMAC0>;
1788 clock-names = "apb_pclk";
1789 #dma-cells = <1>;
1790 };
1791
1792 dmac1: dma-controller@fea30000 {
1793 compatible = "arm,pl330", "arm,primecell";
1794 reg = <0x0 0xfea30000 0x0 0x4000>;
1795 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
1796 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
1797 arm,pl330-periph-burst;
1798 clocks = <&cru ACLK_DMAC1>;
1799 clock-names = "apb_pclk";
1800 #dma-cells = <1>;
1801 };
1802
1803 i2c1: i2c@fea90000 {
1804 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1805 reg = <0x0 0xfea90000 0x0 0x1000>;
1806 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1807 clock-names = "i2c", "pclk";
1808 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
1809 pinctrl-0 = <&i2c1m0_xfer>;
1810 pinctrl-names = "default";
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1813 status = "disabled";
1814 };
1815
1816 i2c2: i2c@feaa0000 {
1817 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1818 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1819 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1820 clock-names = "i2c", "pclk";
1821 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
1822 pinctrl-0 = <&i2c2m0_xfer>;
1823 pinctrl-names = "default";
1824 #address-cells = <1>;
1825 #size-cells = <0>;
1826 status = "disabled";
1827 };
1828
1829 i2c3: i2c@feab0000 {
1830 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1831 reg = <0x0 0xfeab0000 0x0 0x1000>;
1832 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1833 clock-names = "i2c", "pclk";
1834 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
1835 pinctrl-0 = <&i2c3m0_xfer>;
1836 pinctrl-names = "default";
1837 #address-cells = <1>;
1838 #size-cells = <0>;
1839 status = "disabled";
1840 };
1841
1842 i2c4: i2c@feac0000 {
1843 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1844 reg = <0x0 0xfeac0000 0x0 0x1000>;
1845 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1846 clock-names = "i2c", "pclk";
1847 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
1848 pinctrl-0 = <&i2c4m0_xfer>;
1849 pinctrl-names = "default";
1850 #address-cells = <1>;
1851 #size-cells = <0>;
1852 status = "disabled";
1853 };
1854
1855 i2c5: i2c@fead0000 {
1856 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1857 reg = <0x0 0xfead0000 0x0 0x1000>;
1858 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1859 clock-names = "i2c", "pclk";
1860 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
1861 pinctrl-0 = <&i2c5m0_xfer>;
1862 pinctrl-names = "default";
1863 #address-cells = <1>;
1864 #size-cells = <0>;
1865 status = "disabled";
1866 };
1867
1868 timer0: timer@feae0000 {
1869 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1870 reg = <0x0 0xfeae0000 0x0 0x20>;
1871 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
1872 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1873 clock-names = "pclk", "timer";
1874 };
1875
1876 wdt: watchdog@feaf0000 {
1877 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1878 reg = <0x0 0xfeaf0000 0x0 0x100>;
1879 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1880 clock-names = "tclk", "pclk";
1881 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
1882 };
1883
1884 spi0: spi@feb00000 {
1885 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1886 reg = <0x0 0xfeb00000 0x0 0x1000>;
1887 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
1888 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1889 clock-names = "spiclk", "apb_pclk";
1890 dmas = <&dmac0 14>, <&dmac0 15>;
1891 dma-names = "tx", "rx";
1892 num-cs = <2>;
1893 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1894 pinctrl-names = "default";
1895 #address-cells = <1>;
1896 #size-cells = <0>;
1897 status = "disabled";
1898 };
1899
1900 spi1: spi@feb10000 {
1901 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1902 reg = <0x0 0xfeb10000 0x0 0x1000>;
1903 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
1904 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1905 clock-names = "spiclk", "apb_pclk";
1906 dmas = <&dmac0 16>, <&dmac0 17>;
1907 dma-names = "tx", "rx";
1908 num-cs = <2>;
1909 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1910 pinctrl-names = "default";
1911 #address-cells = <1>;
1912 #size-cells = <0>;
1913 status = "disabled";
1914 };
1915
1916 spi2: spi@feb20000 {
1917 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1918 reg = <0x0 0xfeb20000 0x0 0x1000>;
1919 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
1920 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1921 clock-names = "spiclk", "apb_pclk";
1922 dmas = <&dmac1 15>, <&dmac1 16>;
1923 dma-names = "tx", "rx";
1924 num-cs = <2>;
1925 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1926 pinctrl-names = "default";
1927 #address-cells = <1>;
1928 #size-cells = <0>;
1929 status = "disabled";
1930 };
1931
1932 spi3: spi@feb30000 {
1933 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1934 reg = <0x0 0xfeb30000 0x0 0x1000>;
1935 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
1936 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1937 clock-names = "spiclk", "apb_pclk";
1938 dmas = <&dmac1 17>, <&dmac1 18>;
1939 dma-names = "tx", "rx";
1940 num-cs = <2>;
1941 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1942 pinctrl-names = "default";
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1945 status = "disabled";
1946 };
1947
1948 uart1: serial@feb40000 {
1949 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1950 reg = <0x0 0xfeb40000 0x0 0x100>;
1951 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
1952 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1953 clock-names = "baudclk", "apb_pclk";
1954 dmas = <&dmac0 8>, <&dmac0 9>;
1955 dma-names = "tx", "rx";
1956 pinctrl-0 = <&uart1m1_xfer>;
1957 pinctrl-names = "default";
1958 reg-io-width = <4>;
1959 reg-shift = <2>;
1960 status = "disabled";
1961 };
1962
1963 uart2: serial@feb50000 {
1964 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1965 reg = <0x0 0xfeb50000 0x0 0x100>;
1966 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
1967 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1968 clock-names = "baudclk", "apb_pclk";
1969 dmas = <&dmac0 10>, <&dmac0 11>;
1970 dma-names = "tx", "rx";
1971 pinctrl-0 = <&uart2m1_xfer>;
1972 pinctrl-names = "default";
1973 reg-io-width = <4>;
1974 reg-shift = <2>;
1975 status = "disabled";
1976 };
1977
1978 uart3: serial@feb60000 {
1979 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1980 reg = <0x0 0xfeb60000 0x0 0x100>;
1981 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
1982 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1983 clock-names = "baudclk", "apb_pclk";
1984 dmas = <&dmac0 12>, <&dmac0 13>;
1985 dma-names = "tx", "rx";
1986 pinctrl-0 = <&uart3m1_xfer>;
1987 pinctrl-names = "default";
1988 reg-io-width = <4>;
1989 reg-shift = <2>;
1990 status = "disabled";
1991 };
1992
1993 uart4: serial@feb70000 {
1994 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1995 reg = <0x0 0xfeb70000 0x0 0x100>;
1996 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
1997 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1998 clock-names = "baudclk", "apb_pclk";
1999 dmas = <&dmac1 9>, <&dmac1 10>;
2000 dma-names = "tx", "rx";
2001 pinctrl-0 = <&uart4m1_xfer>;
2002 pinctrl-names = "default";
2003 reg-io-width = <4>;
2004 reg-shift = <2>;
2005 status = "disabled";
2006 };
2007
2008 uart5: serial@feb80000 {
2009 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2010 reg = <0x0 0xfeb80000 0x0 0x100>;
2011 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
2012 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
2013 clock-names = "baudclk", "apb_pclk";
2014 dmas = <&dmac1 11>, <&dmac1 12>;
2015 dma-names = "tx", "rx";
2016 pinctrl-0 = <&uart5m1_xfer>;
2017 pinctrl-names = "default";
2018 reg-io-width = <4>;
2019 reg-shift = <2>;
2020 status = "disabled";
2021 };
2022
2023 uart6: serial@feb90000 {
2024 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2025 reg = <0x0 0xfeb90000 0x0 0x100>;
2026 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
2027 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
2028 clock-names = "baudclk", "apb_pclk";
2029 dmas = <&dmac1 13>, <&dmac1 14>;
2030 dma-names = "tx", "rx";
2031 pinctrl-0 = <&uart6m1_xfer>;
2032 pinctrl-names = "default";
2033 reg-io-width = <4>;
2034 reg-shift = <2>;
2035 status = "disabled";
2036 };
2037
2038 uart7: serial@feba0000 {
2039 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2040 reg = <0x0 0xfeba0000 0x0 0x100>;
2041 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
2042 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
2043 clock-names = "baudclk", "apb_pclk";
2044 dmas = <&dmac2 7>, <&dmac2 8>;
2045 dma-names = "tx", "rx";
2046 pinctrl-0 = <&uart7m1_xfer>;
2047 pinctrl-names = "default";
2048 reg-io-width = <4>;
2049 reg-shift = <2>;
2050 status = "disabled";
2051 };
2052
2053 uart8: serial@febb0000 {
2054 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2055 reg = <0x0 0xfebb0000 0x0 0x100>;
2056 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
2057 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
2058 clock-names = "baudclk", "apb_pclk";
2059 dmas = <&dmac2 9>, <&dmac2 10>;
2060 dma-names = "tx", "rx";
2061 pinctrl-0 = <&uart8m1_xfer>;
2062 pinctrl-names = "default";
2063 reg-io-width = <4>;
2064 reg-shift = <2>;
2065 status = "disabled";
2066 };
2067
2068 uart9: serial@febc0000 {
2069 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2070 reg = <0x0 0xfebc0000 0x0 0x100>;
2071 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
2072 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
2073 clock-names = "baudclk", "apb_pclk";
2074 dmas = <&dmac2 11>, <&dmac2 12>;
2075 dma-names = "tx", "rx";
2076 pinctrl-0 = <&uart9m1_xfer>;
2077 pinctrl-names = "default";
2078 reg-io-width = <4>;
2079 reg-shift = <2>;
2080 status = "disabled";
2081 };
2082
2083 pwm4: pwm@febd0000 {
2084 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2085 reg = <0x0 0xfebd0000 0x0 0x10>;
2086 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2087 clock-names = "pwm", "pclk";
2088 pinctrl-0 = <&pwm4m0_pins>;
2089 pinctrl-names = "default";
2090 #pwm-cells = <3>;
2091 status = "disabled";
2092 };
2093
2094 pwm5: pwm@febd0010 {
2095 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2096 reg = <0x0 0xfebd0010 0x0 0x10>;
2097 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2098 clock-names = "pwm", "pclk";
2099 pinctrl-0 = <&pwm5m0_pins>;
2100 pinctrl-names = "default";
2101 #pwm-cells = <3>;
2102 status = "disabled";
2103 };
2104
2105 pwm6: pwm@febd0020 {
2106 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2107 reg = <0x0 0xfebd0020 0x0 0x10>;
2108 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2109 clock-names = "pwm", "pclk";
2110 pinctrl-0 = <&pwm6m0_pins>;
2111 pinctrl-names = "default";
2112 #pwm-cells = <3>;
2113 status = "disabled";
2114 };
2115
2116 pwm7: pwm@febd0030 {
2117 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2118 reg = <0x0 0xfebd0030 0x0 0x10>;
2119 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2120 clock-names = "pwm", "pclk";
2121 pinctrl-0 = <&pwm7m0_pins>;
2122 pinctrl-names = "default";
2123 #pwm-cells = <3>;
2124 status = "disabled";
2125 };
2126
2127 pwm8: pwm@febe0000 {
2128 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2129 reg = <0x0 0xfebe0000 0x0 0x10>;
2130 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2131 clock-names = "pwm", "pclk";
2132 pinctrl-0 = <&pwm8m0_pins>;
2133 pinctrl-names = "default";
2134 #pwm-cells = <3>;
2135 status = "disabled";
2136 };
2137
2138 pwm9: pwm@febe0010 {
2139 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2140 reg = <0x0 0xfebe0010 0x0 0x10>;
2141 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2142 clock-names = "pwm", "pclk";
2143 pinctrl-0 = <&pwm9m0_pins>;
2144 pinctrl-names = "default";
2145 #pwm-cells = <3>;
2146 status = "disabled";
2147 };
2148
2149 pwm10: pwm@febe0020 {
2150 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2151 reg = <0x0 0xfebe0020 0x0 0x10>;
2152 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2153 clock-names = "pwm", "pclk";
2154 pinctrl-0 = <&pwm10m0_pins>;
2155 pinctrl-names = "default";
2156 #pwm-cells = <3>;
2157 status = "disabled";
2158 };
2159
2160 pwm11: pwm@febe0030 {
2161 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2162 reg = <0x0 0xfebe0030 0x0 0x10>;
2163 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2164 clock-names = "pwm", "pclk";
2165 pinctrl-0 = <&pwm11m0_pins>;
2166 pinctrl-names = "default";
2167 #pwm-cells = <3>;
2168 status = "disabled";
2169 };
2170
2171 pwm12: pwm@febf0000 {
2172 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2173 reg = <0x0 0xfebf0000 0x0 0x10>;
2174 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2175 clock-names = "pwm", "pclk";
2176 pinctrl-0 = <&pwm12m0_pins>;
2177 pinctrl-names = "default";
2178 #pwm-cells = <3>;
2179 status = "disabled";
2180 };
2181
2182 pwm13: pwm@febf0010 {
2183 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2184 reg = <0x0 0xfebf0010 0x0 0x10>;
2185 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2186 clock-names = "pwm", "pclk";
2187 pinctrl-0 = <&pwm13m0_pins>;
2188 pinctrl-names = "default";
2189 #pwm-cells = <3>;
2190 status = "disabled";
2191 };
2192
2193 pwm14: pwm@febf0020 {
2194 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2195 reg = <0x0 0xfebf0020 0x0 0x10>;
2196 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2197 clock-names = "pwm", "pclk";
2198 pinctrl-0 = <&pwm14m0_pins>;
2199 pinctrl-names = "default";
2200 #pwm-cells = <3>;
2201 status = "disabled";
2202 };
2203
2204 pwm15: pwm@febf0030 {
2205 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2206 reg = <0x0 0xfebf0030 0x0 0x10>;
2207 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2208 clock-names = "pwm", "pclk";
2209 pinctrl-0 = <&pwm15m0_pins>;
2210 pinctrl-names = "default";
2211 #pwm-cells = <3>;
2212 status = "disabled";
2213 };
2214
2215 tsadc: tsadc@fec00000 {
2216 compatible = "rockchip,rk3588-tsadc";
2217 reg = <0x0 0xfec00000 0x0 0x400>;
2218 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2219 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2220 clock-names = "tsadc", "apb_pclk";
2221 assigned-clocks = <&cru CLK_TSADC>;
2222 assigned-clock-rates = <2000000>;
2223 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2224 reset-names = "tsadc-apb", "tsadc";
2225 rockchip,hw-tshut-temp = <120000>;
2226 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2227 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2228 pinctrl-0 = <&tsadc_gpio_func>;
2229 pinctrl-1 = <&tsadc_shut>;
2230 pinctrl-names = "gpio", "otpout";
2231 #thermal-sensor-cells = <1>;
2232 status = "disabled";
2233 };
2234
2235 saradc: adc@fec10000 {
2236 compatible = "rockchip,rk3588-saradc";
2237 reg = <0x0 0xfec10000 0x0 0x10000>;
2238 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2239 #io-channel-cells = <1>;
2240 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2241 clock-names = "saradc", "apb_pclk";
2242 resets = <&cru SRST_P_SARADC>;
2243 reset-names = "saradc-apb";
2244 status = "disabled";
2245 };
2246
2247 i2c6: i2c@fec80000 {
2248 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2249 reg = <0x0 0xfec80000 0x0 0x1000>;
2250 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2251 clock-names = "i2c", "pclk";
2252 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2253 pinctrl-0 = <&i2c6m0_xfer>;
2254 pinctrl-names = "default";
2255 #address-cells = <1>;
2256 #size-cells = <0>;
2257 status = "disabled";
2258 };
2259
2260 i2c7: i2c@fec90000 {
2261 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2262 reg = <0x0 0xfec90000 0x0 0x1000>;
2263 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2264 clock-names = "i2c", "pclk";
2265 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2266 pinctrl-0 = <&i2c7m0_xfer>;
2267 pinctrl-names = "default";
2268 #address-cells = <1>;
2269 #size-cells = <0>;
2270 status = "disabled";
2271 };
2272
2273 i2c8: i2c@feca0000 {
2274 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2275 reg = <0x0 0xfeca0000 0x0 0x1000>;
2276 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2277 clock-names = "i2c", "pclk";
2278 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2279 pinctrl-0 = <&i2c8m0_xfer>;
2280 pinctrl-names = "default";
2281 #address-cells = <1>;
2282 #size-cells = <0>;
2283 status = "disabled";
2284 };
2285
2286 spi4: spi@fecb0000 {
2287 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2288 reg = <0x0 0xfecb0000 0x0 0x1000>;
2289 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2290 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2291 clock-names = "spiclk", "apb_pclk";
2292 dmas = <&dmac2 13>, <&dmac2 14>;
2293 dma-names = "tx", "rx";
2294 num-cs = <2>;
2295 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2296 pinctrl-names = "default";
2297 #address-cells = <1>;
2298 #size-cells = <0>;
2299 status = "disabled";
2300 };
2301
2302 otp: efuse@fecc0000 {
2303 compatible = "rockchip,rk3588-otp";
2304 reg = <0x0 0xfecc0000 0x0 0x400>;
2305 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2306 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2307 clock-names = "otp", "apb_pclk", "phy", "arb";
2308 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2309 <&cru SRST_OTPC_ARB>;
2310 reset-names = "otp", "apb", "arb";
2311 #address-cells = <1>;
2312 #size-cells = <1>;
2313
2314 cpu_code: cpu-code@2 {
2315 reg = <0x02 0x2>;
2316 };
2317
2318 otp_id: id@7 {
2319 reg = <0x07 0x10>;
2320 };
2321
2322 cpub0_leakage: cpu-leakage@17 {
2323 reg = <0x17 0x1>;
2324 };
2325
2326 cpub1_leakage: cpu-leakage@18 {
2327 reg = <0x18 0x1>;
2328 };
2329
2330 cpul_leakage: cpu-leakage@19 {
2331 reg = <0x19 0x1>;
2332 };
2333
2334 log_leakage: log-leakage@1a {
2335 reg = <0x1a 0x1>;
2336 };
2337
2338 gpu_leakage: gpu-leakage@1b {
2339 reg = <0x1b 0x1>;
2340 };
2341
2342 otp_cpu_version: cpu-version@1c {
2343 reg = <0x1c 0x1>;
2344 bits = <3 3>;
2345 };
2346
2347 npu_leakage: npu-leakage@28 {
2348 reg = <0x28 0x1>;
2349 };
2350
2351 codec_leakage: codec-leakage@29 {
2352 reg = <0x29 0x1>;
2353 };
2354 };
2355
2356 dmac2: dma-controller@fed10000 {
2357 compatible = "arm,pl330", "arm,primecell";
2358 reg = <0x0 0xfed10000 0x0 0x4000>;
2359 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2360 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2361 arm,pl330-periph-burst;
2362 clocks = <&cru ACLK_DMAC2>;
2363 clock-names = "apb_pclk";
2364 #dma-cells = <1>;
2365 };
2366
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]2367 hdptxphy_hdmi0: phy@fed60000 {
2368 compatible = "rockchip,rk3588-hdptx-phy";
2369 reg = <0x0 0xfed60000 0x0 0x2000>;
2370 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
2371 clock-names = "ref", "apb";
2372 #phy-cells = <0>;
2373 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
2374 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
2375 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
2376 <&cru SRST_HDPTX0_LCPLL>;
2377 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
2378 "lcpll";
2379 rockchip,grf = <&hdptxphy0_grf>;
2380 status = "disabled";
2381 };
2382
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2383 combphy0_ps: phy@fee00000 {
2384 compatible = "rockchip,rk3588-naneng-combphy";
2385 reg = <0x0 0xfee00000 0x0 0x100>;
2386 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2387 <&cru PCLK_PHP_ROOT>;
2388 clock-names = "ref", "apb", "pipe";
2389 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2390 assigned-clock-rates = <100000000>;
2391 #phy-cells = <1>;
2392 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2393 reset-names = "phy", "apb";
2394 rockchip,pipe-grf = <&php_grf>;
2395 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2396 status = "disabled";
2397 };
2398
2399 combphy2_psu: phy@fee20000 {
2400 compatible = "rockchip,rk3588-naneng-combphy";
2401 reg = <0x0 0xfee20000 0x0 0x100>;
2402 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2403 <&cru PCLK_PHP_ROOT>;
2404 clock-names = "ref", "apb", "pipe";
2405 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2406 assigned-clock-rates = <100000000>;
2407 #phy-cells = <1>;
2408 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2409 reset-names = "phy", "apb";
2410 rockchip,pipe-grf = <&php_grf>;
2411 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2412 status = "disabled";
2413 };
2414
2415 system_sram2: sram@ff001000 {
2416 compatible = "mmio-sram";
2417 reg = <0x0 0xff001000 0x0 0xef000>;
2418 ranges = <0x0 0x0 0xff001000 0xef000>;
2419 #address-cells = <1>;
2420 #size-cells = <1>;
2421 };
2422
2423 pinctrl: pinctrl {
2424 compatible = "rockchip,rk3588-pinctrl";
2425 ranges;
2426 rockchip,grf = <&ioc>;
2427 #address-cells = <2>;
2428 #size-cells = <2>;
2429
2430 gpio0: gpio@fd8a0000 {
2431 compatible = "rockchip,gpio-bank";
2432 reg = <0x0 0xfd8a0000 0x0 0x100>;
2433 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2434 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2435 gpio-controller;
2436 gpio-ranges = <&pinctrl 0 0 32>;
2437 interrupt-controller;
2438 #gpio-cells = <2>;
2439 #interrupt-cells = <2>;
2440 };
2441
2442 gpio1: gpio@fec20000 {
2443 compatible = "rockchip,gpio-bank";
2444 reg = <0x0 0xfec20000 0x0 0x100>;
2445 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2446 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2447 gpio-controller;
2448 gpio-ranges = <&pinctrl 0 32 32>;
2449 interrupt-controller;
2450 #gpio-cells = <2>;
2451 #interrupt-cells = <2>;
2452 };
2453
2454 gpio2: gpio@fec30000 {
2455 compatible = "rockchip,gpio-bank";
2456 reg = <0x0 0xfec30000 0x0 0x100>;
2457 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2458 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2459 gpio-controller;
2460 gpio-ranges = <&pinctrl 0 64 32>;
2461 interrupt-controller;
2462 #gpio-cells = <2>;
2463 #interrupt-cells = <2>;
2464 };
2465
2466 gpio3: gpio@fec40000 {
2467 compatible = "rockchip,gpio-bank";
2468 reg = <0x0 0xfec40000 0x0 0x100>;
2469 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2470 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2471 gpio-controller;
2472 gpio-ranges = <&pinctrl 0 96 32>;
2473 interrupt-controller;
2474 #gpio-cells = <2>;
2475 #interrupt-cells = <2>;
2476 };
2477
2478 gpio4: gpio@fec50000 {
2479 compatible = "rockchip,gpio-bank";
2480 reg = <0x0 0xfec50000 0x0 0x100>;
2481 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2482 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2483 gpio-controller;
2484 gpio-ranges = <&pinctrl 0 128 32>;
2485 interrupt-controller;
2486 #gpio-cells = <2>;
2487 #interrupt-cells = <2>;
2488 };
2489 };
2490
2491 av1d: video-codec@fdc70000 {
2492 compatible = "rockchip,rk3588-av1-vpu";
2493 reg = <0x0 0xfdc70000 0x0 0x800>;
2494 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
2495 interrupt-names = "vdpu";
2496 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
2497 assigned-clock-rates = <400000000>, <400000000>;
2498 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
2499 clock-names = "aclk", "hclk";
2500 power-domains = <&power RK3588_PD_AV1>;
2501 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
2502 };
2503};
2504
2505#include "rk3588s-pinctrl.dtsi"