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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm64 / freescale / imx8mm-evk.dtsi
blob: bd5b365867fda26d130462cccdf9fda8ee2b6293 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9#include <dt-bindings/usb/pd.h>
10#include "imx8mm.dtsi"
11
12/ {
13 chosen {
14 stdout-path = &uart2;
15 };
16
17 memory@40000000 {
18 device_type = "memory";
19 reg = <0x0 0x40000000 0 0x80000000>;
20 };
21
22 hdmi-connector {
23 compatible = "hdmi-connector";
24 label = "hdmi";
25 type = "a";
26
27 port {
28 hdmi_connector_in: endpoint {
29 remote-endpoint = <&adv7535_out>;
30 };
31 };
32 };
33
34 leds {
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_led>;
38
39 status {
40 label = "status";
41 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
42 default-state = "on";
43 };
44 };
45
46 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <100000000>;
50 };
51
52 reg_pcie0: regulator-pcie {
53 compatible = "regulator-fixed";
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_pcie0_reg>;
56 regulator-name = "MPCIE_3V3";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
60 enable-active-high;
61 };
62
63 reg_usdhc2_vmmc: regulator-usdhc2 {
64 compatible = "regulator-fixed";
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
67 regulator-name = "VSD_3V3";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
71 off-on-delay-us = <20000>;
72 enable-active-high;
73 };
74
75 reg_vddext_3v3: regulator-vddext-3v3 {
76 compatible = "regulator-fixed";
77 regulator-name = "VDDEXT_3V3";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 };
81
82 backlight: backlight {
83 compatible = "pwm-backlight";
84 pwms = <&pwm1 0 5000000 0>;
85 brightness-levels = <0 255>;
86 num-interpolated-steps = <255>;
87 default-brightness-level = <250>;
88 };
89
90 ir-receiver {
91 compatible = "gpio-ir-receiver";
92 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_ir>;
95 linux,autosuspend-period = <125>;
96 };
97
98 audio_codec_bt_sco: audio-codec-bt-sco {
99 compatible = "linux,bt-sco";
100 #sound-dai-cells = <1>;
101 };
102
103 wm8524: audio-codec {
104 #sound-dai-cells = <0>;
105 compatible = "wlf,wm8524";
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_gpio_wlf>;
108 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
109 };
110
111 sound-bt-sco {
112 compatible = "simple-audio-card";
113 simple-audio-card,name = "bt-sco-audio";
114 simple-audio-card,format = "dsp_a";
115 simple-audio-card,bitclock-inversion;
116 simple-audio-card,frame-master = <&btcpu>;
117 simple-audio-card,bitclock-master = <&btcpu>;
118
119 btcpu: simple-audio-card,cpu {
120 sound-dai = <&sai2>;
121 dai-tdm-slot-num = <2>;
122 dai-tdm-slot-width = <16>;
123 };
124
125 simple-audio-card,codec {
126 sound-dai = <&audio_codec_bt_sco 1>;
127 };
128 };
129
130 sound-wm8524 {
131 compatible = "simple-audio-card";
132 simple-audio-card,name = "wm8524-audio";
133 simple-audio-card,format = "i2s";
134 simple-audio-card,frame-master = <&cpudai>;
135 simple-audio-card,bitclock-master = <&cpudai>;
136 simple-audio-card,widgets =
137 "Line", "Left Line Out Jack",
138 "Line", "Right Line Out Jack";
139 simple-audio-card,routing =
140 "Left Line Out Jack", "LINEVOUTL",
141 "Right Line Out Jack", "LINEVOUTR";
142
143 cpudai: simple-audio-card,cpu {
144 sound-dai = <&sai3>;
145 dai-tdm-slot-num = <2>;
146 dai-tdm-slot-width = <32>;
147 };
148
149 simple-audio-card,codec {
150 sound-dai = <&wm8524>;
151 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
152 };
153 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]154
155 sound-micfil {
156 compatible = "fsl,imx-audio-card";
157 model = "micfil-audio";
158
159 pri-dai-link {
160 link-name = "micfil hifi";
161 format = "i2s";
162
163 cpu {
164 sound-dai = <&micfil>;
165 };
166 };
167 };
168
169 sound-spdif {
170 compatible = "fsl,imx-audio-spdif";
171 model = "imx-spdif";
172 spdif-controller = <&spdif1>;
173 spdif-out;
174 spdif-in;
175 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]176};
177
178&A53_0 {
179 cpu-supply = <&buck2_reg>;
180};
181
182&A53_1 {
183 cpu-supply = <&buck2_reg>;
184};
185
186&A53_2 {
187 cpu-supply = <&buck2_reg>;
188};
189
190&A53_3 {
191 cpu-supply = <&buck2_reg>;
192};
193
194&fec1 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_fec1>;
197 phy-mode = "rgmii-id";
198 phy-handle = <&ethphy0>;
199 fsl,magic-packet;
200 status = "okay";
201
202 mdio {
203 #address-cells = <1>;
204 #size-cells = <0>;
205
206 ethphy0: ethernet-phy@0 {
207 compatible = "ethernet-phy-ieee802.3-c22";
208 reg = <0>;
209 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
210 reset-assert-us = <10000>;
211 qca,disable-smarteee;
212 vddio-supply = <&vddio>;
213
214 vddio: vddio-regulator {
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <1800000>;
217 };
218 };
219 };
220};
221
222&i2c1 {
223 clock-frequency = <400000>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_i2c1>;
226 status = "okay";
227
228 pmic@4b {
229 compatible = "rohm,bd71847";
230 reg = <0x4b>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_pmic>;
233 interrupt-parent = <&gpio1>;
234 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
235 rohm,reset-snvs-powered;
236
237 #clock-cells = <0>;
238 clocks = <&osc_32k>;
239 clock-output-names = "clk-32k-out";
240
241 regulators {
242 buck1_reg: BUCK1 {
243 regulator-name = "buck1";
244 regulator-min-microvolt = <700000>;
245 regulator-max-microvolt = <1300000>;
246 regulator-boot-on;
247 regulator-always-on;
248 regulator-ramp-delay = <1250>;
249 };
250
251 buck2_reg: BUCK2 {
252 regulator-name = "buck2";
253 regulator-min-microvolt = <700000>;
254 regulator-max-microvolt = <1300000>;
255 regulator-boot-on;
256 regulator-always-on;
257 regulator-ramp-delay = <1250>;
258 rohm,dvs-run-voltage = <1000000>;
259 rohm,dvs-idle-voltage = <900000>;
260 };
261
262 buck3_reg: BUCK3 {
263 // BUCK5 in datasheet
264 regulator-name = "buck3";
265 regulator-min-microvolt = <700000>;
266 regulator-max-microvolt = <1350000>;
267 regulator-boot-on;
268 regulator-always-on;
269 };
270
271 buck4_reg: BUCK4 {
272 // BUCK6 in datasheet
273 regulator-name = "buck4";
274 regulator-min-microvolt = <3000000>;
275 regulator-max-microvolt = <3300000>;
276 regulator-boot-on;
277 regulator-always-on;
278 };
279
280 buck5_reg: BUCK5 {
281 // BUCK7 in datasheet
282 regulator-name = "buck5";
283 regulator-min-microvolt = <1605000>;
284 regulator-max-microvolt = <1995000>;
285 regulator-boot-on;
286 regulator-always-on;
287 };
288
289 buck6_reg: BUCK6 {
290 // BUCK8 in datasheet
291 regulator-name = "buck6";
292 regulator-min-microvolt = <800000>;
293 regulator-max-microvolt = <1400000>;
294 regulator-boot-on;
295 regulator-always-on;
296 };
297
298 ldo1_reg: LDO1 {
299 regulator-name = "ldo1";
300 regulator-min-microvolt = <1600000>;
301 regulator-max-microvolt = <3300000>;
302 regulator-boot-on;
303 regulator-always-on;
304 };
305
306 ldo2_reg: LDO2 {
307 regulator-name = "ldo2";
308 regulator-min-microvolt = <800000>;
309 regulator-max-microvolt = <900000>;
310 regulator-boot-on;
311 regulator-always-on;
312 };
313
314 ldo3_reg: LDO3 {
315 regulator-name = "ldo3";
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <3300000>;
318 regulator-boot-on;
319 regulator-always-on;
320 };
321
322 ldo4_reg: LDO4 {
323 regulator-name = "ldo4";
324 regulator-min-microvolt = <900000>;
325 regulator-max-microvolt = <1800000>;
326 regulator-boot-on;
327 regulator-always-on;
328 };
329
330 ldo6_reg: LDO6 {
331 regulator-name = "ldo6";
332 regulator-min-microvolt = <900000>;
333 regulator-max-microvolt = <1800000>;
334 regulator-boot-on;
335 regulator-always-on;
336 };
337 };
338 };
339};
340
341&i2c2 {
342 clock-frequency = <400000>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_i2c2>;
345 status = "okay";
346
347 hdmi@3d {
348 compatible = "adi,adv7535";
349 reg = <0x3d>;
350 interrupt-parent = <&gpio1>;
351 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
352 adi,dsi-lanes = <4>;
353 avdd-supply = <&buck5_reg>;
354 dvdd-supply = <&buck5_reg>;
355 pvdd-supply = <&buck5_reg>;
356 a2vdd-supply = <&buck5_reg>;
357 v3p3-supply = <&reg_vddext_3v3>;
358 v1p2-supply = <&buck5_reg>;
359
360 ports {
361 #address-cells = <1>;
362 #size-cells = <0>;
363
364 port@0 {
365 reg = <0>;
366
367 adv7535_in: endpoint {
368 remote-endpoint = <&dsi_out>;
369 };
370 };
371
372 port@1 {
373 reg = <1>;
374
375 adv7535_out: endpoint {
376 remote-endpoint = <&hdmi_connector_in>;
377 };
378 };
379
380 };
381 };
382
383 ptn5110: tcpc@50 {
384 compatible = "nxp,ptn5110";
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_typec1>;
387 reg = <0x50>;
388 interrupt-parent = <&gpio2>;
389 interrupts = <11 8>;
390 status = "okay";
391
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]392 typec1_con: connector {
393 compatible = "usb-c-connector";
394 label = "USB-C";
395 power-role = "dual";
396 data-role = "dual";
397 try-power-role = "sink";
398 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
399 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
400 PDO_VAR(5000, 20000, 3000)>;
401 op-sink-microwatt = <15000000>;
402 self-powered;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]403
404 port {
405 typec1_dr_sw: endpoint {
406 remote-endpoint = <&usb1_drd_sw>;
407 };
408 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]409 };
410 };
411};
412
413
414&csi {
415 status = "okay";
416};
417
418&i2c3 {
419 clock-frequency = <400000>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_i2c3>;
422 status = "okay";
423
424 pca6416: gpio@20 {
425 compatible = "nxp,pca6416";
426 reg = <0x20>;
427 gpio-controller;
428 #gpio-cells = <2>;
429 vcc-supply = <&buck4_reg>;
430 };
431
432 camera@3c {
433 compatible = "ovti,ov5640";
434 reg = <0x3c>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_camera>;
437 clocks = <&clk IMX8MM_CLK_CLKO1>;
438 clock-names = "xclk";
439 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
440 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
441 assigned-clock-rates = <24000000>;
442 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
443 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
444
445 port {
446 ov5640_to_mipi_csi2: endpoint {
447 remote-endpoint = <&imx8mm_mipi_csi_in>;
448 clock-lanes = <0>;
449 data-lanes = <1 2>;
450 };
451 };
452 };
453};
454
455&lcdif {
456 status = "okay";
457};
458
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]459&micfil {
460 #sound-dai-cells = <0>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_pdm>;
463 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
464 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
465 assigned-clock-rates = <196608000>;
466 status = "okay";
467};
468
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]469&mipi_csi {
470 status = "okay";
471
472 ports {
473 port@0 {
474 imx8mm_mipi_csi_in: endpoint {
475 remote-endpoint = <&ov5640_to_mipi_csi2>;
476 data-lanes = <1 2>;
477 };
478 };
479 };
480};
481
482&mipi_dsi {
483 samsung,esc-clock-frequency = <10000000>;
484 status = "okay";
485
486 ports {
487 port@1 {
488 reg = <1>;
489
490 dsi_out: endpoint {
491 remote-endpoint = <&adv7535_in>;
492 data-lanes = <1 2 3 4>;
493 };
494 };
495 };
496};
497
498&pcie_phy {
499 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
500 fsl,tx-deemph-gen1 = <0x2d>;
501 fsl,tx-deemph-gen2 = <0xf>;
502 clocks = <&pcie0_refclk>;
503 status = "okay";
504};
505
506&pcie0 {
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_pcie0>;
509 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
510 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
511 <&clk IMX8MM_CLK_PCIE1_AUX>;
512 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
513 <&clk IMX8MM_CLK_PCIE1_CTRL>;
514 assigned-clock-rates = <10000000>, <250000000>;
515 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
516 <&clk IMX8MM_SYS_PLL2_250M>;
517 vpcie-supply = <&reg_pcie0>;
518 status = "okay";
519};
520
521&sai2 {
522 #sound-dai-cells = <0>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_sai2>;
525 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
526 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
527 assigned-clock-rates = <24576000>;
528 status = "okay";
529};
530
531&sai3 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_sai3>;
534 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
535 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
536 assigned-clock-rates = <24576000>;
537 status = "okay";
538};
539
540&snvs_pwrkey {
541 status = "okay";
542};
543
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]544&spdif1 {
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_spdif1>;
547 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
548 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
549 assigned-clock-rates = <24576000>;
550 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
551 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
552 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
553 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
554 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
555 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
556 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
557 "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba",
558 "pll8k", "pll11k";
559 status = "okay";
560};
561
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]562&uart2 { /* console */
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_uart2>;
565 status = "okay";
566};
567
568&usbphynop1 {
569 wakeup-source;
570};
571
572&usbotg1 {
573 dr_mode = "otg";
574 hnp-disable;
575 srp-disable;
576 adp-disable;
577 usb-role-switch;
578 disable-over-current;
579 samsung,picophy-pre-emp-curr-control = <3>;
580 samsung,picophy-dc-vol-level-adjust = <7>;
581 status = "okay";
582
583 port {
584 usb1_drd_sw: endpoint {
585 remote-endpoint = <&typec1_dr_sw>;
586 };
587 };
588};
589
590&usdhc2 {
591 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
592 assigned-clock-rates = <200000000>;
593 pinctrl-names = "default", "state_100mhz", "state_200mhz";
594 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
595 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
596 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
597 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
598 bus-width = <4>;
599 vmmc-supply = <&reg_usdhc2_vmmc>;
600 status = "okay";
601};
602
603&wdog1 {
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_wdog>;
606 fsl,ext-reset-output;
607 status = "okay";
608};
609
610&pwm1 {
611 pinctrl-names = "default";
612 pinctrl-0 = <&pinctrl_backlight>;
613 status = "okay";
614};
615
616&iomuxc {
617 pinctrl_fec1: fec1grp {
618 fsl,pins = <
619 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
620 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
621 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
622 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
623 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
624 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
625 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
626 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
627 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
628 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
629 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
630 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
631 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
632 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
633 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
634 >;
635 };
636
637 pinctrl_gpio_led: gpioledgrp {
638 fsl,pins = <
639 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
640 >;
641 };
642
643 pinctrl_ir: irgrp {
644 fsl,pins = <
645 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
646 >;
647 };
648
649 pinctrl_gpio_wlf: gpiowlfgrp {
650 fsl,pins = <
651 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
652 >;
653 };
654
655 pinctrl_i2c1: i2c1grp {
656 fsl,pins = <
657 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
658 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
659 >;
660 };
661
662 pinctrl_i2c2: i2c2grp {
663 fsl,pins = <
664 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
665 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
666 >;
667 };
668
669 pinctrl_i2c3: i2c3grp {
670 fsl,pins = <
671 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
672 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
673 >;
674 };
675
676 pinctrl_pcie0: pcie0grp {
677 fsl,pins = <
678 MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
679 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
680 >;
681 };
682
683 pinctrl_pcie0_reg: pcie0reggrp {
684 fsl,pins = <
685 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
686 >;
687 };
688
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]689 pinctrl_pdm: pdmgrp {
690 fsl,pins = <
691 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
692 MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
693 MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
694 MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
695 MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
696 MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
697 MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
698 >;
699 };
700
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]701 pinctrl_pmic: pmicirqgrp {
702 fsl,pins = <
703 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
704 >;
705 };
706
707 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
708 fsl,pins = <
709 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
710 >;
711 };
712
713 pinctrl_sai2: sai2grp {
714 fsl,pins = <
715 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
716 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
717 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
718 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
719 >;
720 };
721
722 pinctrl_sai3: sai3grp {
723 fsl,pins = <
724 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
725 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
726 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
727 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
728 >;
729 };
730
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]731 pinctrl_spdif1: spdif1grp {
732 fsl,pins = <
733 MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
734 MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
735 >;
736 };
737
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]738 pinctrl_typec1: typec1grp {
739 fsl,pins = <
740 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
741 >;
742 };
743
744 pinctrl_uart2: uart2grp {
745 fsl,pins = <
746 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
747 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
748 >;
749 };
750
751 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
752 fsl,pins = <
753 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
754 >;
755 };
756
757 pinctrl_usdhc2: usdhc2grp {
758 fsl,pins = <
759 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
760 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
761 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
762 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
763 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
764 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
765 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
766 >;
767 };
768
769 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
770 fsl,pins = <
771 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
772 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
773 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
774 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
775 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
776 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
777 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
778 >;
779 };
780
781 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
782 fsl,pins = <
783 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
784 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
785 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
786 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
787 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
788 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
789 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
790 >;
791 };
792
793 pinctrl_wdog: wdoggrp {
794 fsl,pins = <
795 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
796 >;
797 };
798
799 pinctrl_backlight: backlightgrp {
800 fsl,pins = <
801 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
802 >;
803 };
804
805 pinctrl_camera: cameragrp {
806 fsl,pins = <
807 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
808 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
809 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
810 >;
811 };
812};