| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2021 NXP |
| 4 | * Dong Aisheng <aisheng.dong@nxp.com> |
| 5 | */ |
| 6 | |
| 7 | vpu: vpu@2c000000 { |
| 8 | #address-cells = <1>; |
| 9 | #size-cells = <1>; |
| 10 | ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; |
| 11 | reg = <0 0x2c000000 0 0x1000000>; |
| 12 | power-domains = <&pd IMX_SC_R_VPU>; |
| 13 | status = "disabled"; |
| 14 | |
| 15 | mu_m0: mailbox@2d000000 { |
| 16 | compatible = "fsl,imx6sx-mu"; |
| 17 | reg = <0x2d000000 0x20000>; |
| 18 | interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; |
| 19 | #mbox-cells = <2>; |
| 20 | power-domains = <&pd IMX_SC_R_VPU_MU_0>; |
| 21 | status = "disabled"; |
| 22 | }; |
| 23 | |
| 24 | mu1_m0: mailbox@2d020000 { |
| 25 | compatible = "fsl,imx6sx-mu"; |
| 26 | reg = <0x2d020000 0x20000>; |
| 27 | interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; |
| 28 | #mbox-cells = <2>; |
| 29 | power-domains = <&pd IMX_SC_R_VPU_MU_1>; |
| 30 | status = "disabled"; |
| 31 | }; |
| 32 | |
| 33 | mu2_m0: mailbox@2d040000 { |
| 34 | compatible = "fsl,imx6sx-mu"; |
| 35 | reg = <0x2d040000 0x20000>; |
| 36 | interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; |
| 37 | #mbox-cells = <2>; |
| 38 | power-domains = <&pd IMX_SC_R_VPU_MU_2>; |
| 39 | status = "disabled"; |
| 40 | }; |
| 41 | |
| 42 | vpu_core0: vpu-core@2d080000 { |
| 43 | reg = <0x2d080000 0x10000>; |
| 44 | compatible = "nxp,imx8q-vpu-decoder"; |
| 45 | power-domains = <&pd IMX_SC_R_VPU_DEC_0>; |
| 46 | mbox-names = "tx0", "tx1", "rx"; |
| 47 | mboxes = <&mu_m0 0 0>, |
| 48 | <&mu_m0 0 1>, |
| 49 | <&mu_m0 1 0>; |
| 50 | status = "disabled"; |
| 51 | }; |
| 52 | |
| 53 | vpu_core1: vpu-core@2d090000 { |
| 54 | reg = <0x2d090000 0x10000>; |
| 55 | compatible = "nxp,imx8q-vpu-encoder"; |
| 56 | power-domains = <&pd IMX_SC_R_VPU_ENC_0>; |
| 57 | mbox-names = "tx0", "tx1", "rx"; |
| 58 | mboxes = <&mu1_m0 0 0>, |
| 59 | <&mu1_m0 0 1>, |
| 60 | <&mu1_m0 1 0>; |
| 61 | status = "disabled"; |
| 62 | }; |
| 63 | |
| 64 | vpu_core2: vpu-core@2d0a0000 { |
| 65 | reg = <0x2d0a0000 0x10000>; |
| 66 | compatible = "nxp,imx8q-vpu-encoder"; |
| 67 | power-domains = <&pd IMX_SC_R_VPU_ENC_1>; |
| 68 | mbox-names = "tx0", "tx1", "rx"; |
| 69 | mboxes = <&mu2_m0 0 0>, |
| 70 | <&mu2_m0 0 1>, |
| 71 | <&mu2_m0 1 0>; |
| 72 | status = "disabled"; |
| 73 | }; |
| 74 | }; |