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Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Fast Models
4 *
5 * Architecture Envelope Model (AEM) ARMv8-A
6 * ARMAEMv8AMPCT
7 *
8 * RTSM_VE_AEMv8A.lisa
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/memreserve/ 0x80000000 0x00010000;
16
17#include "rtsm_ve-motherboard.dtsi"
18
19/ {
20 model = "RTSM_VE_AEMv8A";
21 compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 chosen { };
27
28 aliases {
29 serial0 = &v2m_serial0;
30 serial1 = &v2m_serial1;
31 serial2 = &v2m_serial2;
32 serial3 = &v2m_serial3;
33 };
34
35 cpus {
36 #address-cells = <2>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 device_type = "cpu";
41 compatible = "arm,armv8";
42 reg = <0x0 0x0>;
43 enable-method = "spin-table";
44 cpu-release-addr = <0x0 0x8000fff8>;
45 next-level-cache = <&L2_0>;
46 };
47 cpu@1 {
48 device_type = "cpu";
49 compatible = "arm,armv8";
50 reg = <0x0 0x1>;
51 enable-method = "spin-table";
52 cpu-release-addr = <0x0 0x8000fff8>;
53 next-level-cache = <&L2_0>;
54 };
55 cpu@2 {
56 device_type = "cpu";
57 compatible = "arm,armv8";
58 reg = <0x0 0x2>;
59 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x8000fff8>;
61 next-level-cache = <&L2_0>;
62 };
63 cpu@3 {
64 device_type = "cpu";
65 compatible = "arm,armv8";
66 reg = <0x0 0x3>;
67 enable-method = "spin-table";
68 cpu-release-addr = <0x0 0x8000fff8>;
69 next-level-cache = <&L2_0>;
70 };
71
72 L2_0: l2-cache0 {
73 compatible = "cache";
74 cache-level = <2>;
75 cache-unified;
76 };
77 };
78
79 memory@80000000 {
80 device_type = "memory";
81 reg = <0x00000000 0x80000000 0 0x80000000>,
82 <0x00000008 0x80000000 0 0x80000000>;
83 };
84
85 reserved-memory {
86 #address-cells = <2>;
87 #size-cells = <2>;
88 ranges;
89
90 /* Chipselect 2,00000000 is physically at 0x18000000 */
91 vram: vram@18000000 {
92 /* 8 MB of designated video RAM */
93 compatible = "shared-dma-pool";
94 reg = <0x00000000 0x18000000 0 0x00800000>;
95 no-map;
96 };
97 };
98
99 gic: interrupt-controller@2c001000 {
100 compatible = "arm,gic-400", "arm,cortex-a15-gic";
101 #interrupt-cells = <3>;
102 #address-cells = <0>;
103 interrupt-controller;
104 reg = <0x0 0x2c001000 0 0x1000>,
105 <0x0 0x2c002000 0 0x2000>,
106 <0x0 0x2c004000 0 0x2000>,
107 <0x0 0x2c006000 0 0x2000>;
108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
109 };
110
111 timer {
112 compatible = "arm,armv8-timer";
113 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
117 clock-frequency = <100000000>;
118 };
119
120 pmu {
121 compatible = "arm,armv8-pmuv3";
122 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
126 };
127
128 panel {
129 compatible = "arm,rtsm-display";
130 port {
131 panel_in: endpoint {
132 remote-endpoint = <&clcd_pads>;
133 };
134 };
135 };
136
137 bus@8000000 {
138 #interrupt-cells = <1>;
139 interrupt-map-mask = <0 0 63>;
140 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
148 <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
149 <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
152 <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
153 <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
154 <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
155 <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
156 <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
157 <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
158 <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
159 <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
160 <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
161 <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
162 <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
163 <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
164 <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
165 <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
166 <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
167 <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
168 <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
169 <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
170 <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
171 <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
172 <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
173 <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
174 <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
175 <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
176 <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
177 <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
178 <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
179 <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
180 <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
181 <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
183 };
184};