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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm / ti / omap / am335x-lxm.dts
blob: be27b5a21b2c60eff996d62fdabfa1371bba6644 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com
4 */
5/dts-v1/;
6
7#include "am33xx.dtsi"
8
9/ {
10 model = "NovaTech OrionLXm";
11 compatible = "novatech,am335x-lxm", "ti,am33xx";
12
13 cpus {
14 cpu@0 {
15 cpu0-supply = <&vdd1_reg>;
16 };
17 };
18
19 memory@80000000 {
20 device_type = "memory";
21 reg = <0x80000000 0x20000000>; /* 512 MB */
22 };
23
24 /* Power supply provides a fixed 5V @2A */
25 vbat: fixedregulator0 {
26 compatible = "regulator-fixed";
27 regulator-name = "vbat";
28 regulator-min-microvolt = <5000000>;
29 regulator-max-microvolt = <5000000>;
30 regulator-boot-on;
31 };
32
33 /* Power supply provides a fixed 3.3V @3A */
34 vmmcsd_fixed: fixedregulator1 {
35 compatible = "regulator-fixed";
36 regulator-name = "vmmcsd_fixed";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-boot-on;
40 };
41};
42
43&am33xx_pinmux {
44 mmc1_pins: mmc1-pins {
45 pinctrl-single,pins = <
46 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
47 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
48 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
49 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
50 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
51 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
52 >;
53 };
54
55 i2c0_pins: i2c0-pins {
56 pinctrl-single,pins = <
57 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
58 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
59 >;
60 };
61
62 cpsw_default: cpsw-default-pins {
63 pinctrl-single,pins = <
64 /* Slave 1 */
65 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */
66 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */
67 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */
68 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */
69 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */
70 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */
71 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */
72 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */
73 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
74
75 /* Slave 2 */
76 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
77 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
78 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
79 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
80 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
81 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
82 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
83 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */
84 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
85 >;
86 };
87
88 cpsw_sleep: cpsw-sleep-pins {
89 pinctrl-single,pins = <
90 /* Slave 1 reset value */
91 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */
92 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */
93 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */
94 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */
95 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */
96 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */
97 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */
98 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */
99 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */
100
101 /* Slave 2 reset value*/
102 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */
103 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */
104 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */
105 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */
106 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */
107 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */
108 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */
109 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */
110 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */
111 >;
112 };
113
114 davinci_mdio_default: davinci-mdio-default-pins {
115 pinctrl-single,pins = <
116 /* MDIO */
117 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
118 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
119 >;
120 };
121
122 davinci_mdio_sleep: davinci-mdio-sleep-pins {
123 pinctrl-single,pins = <
124 /* MDIO reset value */
125 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
126 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
127 >;
128 };
129
130 emmc_pins: emmc-pins {
131 pinctrl-single,pins = <
132 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
133 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
134 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
135 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
136 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
137 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
138 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
139 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
140 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
141 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
142 >;
143 };
144
145 uart0_pins: uart0-pins {
146 pinctrl-single,pins = <
147 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
148 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
149 >;
150 };
151};
152
153&i2c0 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&i2c0_pins>;
156
157 status = "okay";
158 clock-frequency = <400000>;
159
160 serial_config1: serial_config1@20 {
161 compatible = "nxp,pca9539";
162 reg = <0x20>;
163 gpio-controller;
164 #gpio-cells = <2>;
165 };
166
167 serial_config2: serial_config2@21 {
168 compatible = "nxp,pca9539";
169 reg = <0x21>;
170 gpio-controller;
171 #gpio-cells = <2>;
172 };
173
174 tps: tps@2d {
175 compatible = "ti,tps65910";
176 reg = <0x2d>;
177 };
178};
179
180/include/ "../../tps65910.dtsi"
181
182&tps {
183 vcc1-supply = <&vbat>;
184 vcc2-supply = <&vbat>;
185 vcc3-supply = <&vbat>;
186 vcc4-supply = <&vbat>;
187 vcc5-supply = <&vbat>;
188 vcc6-supply = <&vbat>;
189 vcc7-supply = <&vbat>;
190 vccio-supply = <&vbat>;
191
192 regulators {
193 /* vrtc - unused */
194
195 vio_reg: regulator@1 {
196 regulator-name = "vio_1v5,ddr";
197 regulator-min-microvolt = <1500000>;
198 regulator-max-microvolt = <1500000>;
199 regulator-boot-on;
200 regulator-always-on;
201 };
202
203 vdd1_reg: regulator@2 {
204 regulator-name = "vdd1,mpu";
205 regulator-min-microvolt = <600000>;
206 regulator-max-microvolt = <1500000>;
207 regulator-boot-on;
208 regulator-always-on;
209 };
210
211 vdd2_reg: regulator@3 {
212 regulator-name = "vdd2_1v1,core";
213 regulator-min-microvolt = <1100000>;
214 regulator-max-microvolt = <1100000>;
215 regulator-boot-on;
216 regulator-always-on;
217 };
218
219 /* vdd3 - unused */
220
221 /* vdig1 - unused */
222
223 vdig2_reg: regulator@6 {
224 regulator-name = "vdig2_1v8,vdds_pll";
225 regulator-min-microvolt = <1800000>;
226 regulator-max-microvolt = <1800000>;
227 regulator-boot-on;
228 regulator-always-on;
229 };
230
231 /* vpll - unused */
232
233 vdac_reg: regulator@8 {
234 regulator-name = "vdac_1v8,vdds";
235 regulator-min-microvolt = <1800000>;
236 regulator-max-microvolt = <1800000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 vaux1_reg: regulator@9 {
242 regulator-name = "vaux1_1v8,usb";
243 regulator-min-microvolt = <1800000>;
244 regulator-max-microvolt = <1800000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248
249 vaux2_reg: regulator@10 {
250 regulator-name = "vaux2_3v3,io";
251 regulator-min-microvolt = <3300000>;
252 regulator-max-microvolt = <3300000>;
253 regulator-boot-on;
254 regulator-always-on;
255 };
256
257 vaux33_reg: regulator@11 {
258 regulator-name = "vaux33_3v3,usb";
259 regulator-min-microvolt = <3300000>;
260 regulator-max-microvolt = <3300000>;
261 regulator-boot-on;
262 regulator-always-on;
263 };
264
265 vmmc_reg: regulator@12 {
266 regulator-name = "vmmc_3v3,io";
267 regulator-min-microvolt = <3300000>;
268 regulator-max-microvolt = <3300000>;
269 regulator-boot-on;
270 regulator-always-on;
271 };
272 };
273};
274
275&sham {
276 status = "okay";
277};
278
279&aes {
280 status = "okay";
281};
282
283&uart0 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&uart0_pins>;
286
287 status = "okay";
288};
289
290&usb0 {
291 dr_mode = "host";
292};
293
294&usb1 {
295 dr_mode = "host";
296};
297
298&cpsw_port1 {
299 phy-handle = <&ethphy0>;
300 phy-mode = "rmii";
301 ti,dual-emac-pvid = <2>;
302};
303
304&cpsw_port2 {
305 phy-handle = <&ethphy1>;
306 phy-mode = "rmii";
307 ti,dual-emac-pvid = <3>;
308};
309
310&mac_sw {
311 pinctrl-names = "default", "sleep";
312 pinctrl-0 = <&cpsw_default>;
313 pinctrl-1 = <&cpsw_sleep>;
314 status = "okay";
315};
316
317&davinci_mdio_sw {
318 pinctrl-names = "default", "sleep";
319 pinctrl-0 = <&davinci_mdio_default>;
320 pinctrl-1 = <&davinci_mdio_sleep>;
321
322 ethphy0: ethernet-phy@5 {
323 reg = <5>;
324 };
325
326 ethphy1: ethernet-phy@4 {
327 reg = <4>;
328 };
329};
330
331&mmc1 {
332 pinctrl-names = "default";
333 pinctrl-0 = <&mmc1_pins>;
334 vmmc-supply = <&vmmcsd_fixed>;
335 bus-width = <4>;
336 status = "okay";
337};
338
339&mmc2 {
340 pinctrl-names = "default";
341 pinctrl-0 = <&emmc_pins>;
342 vmmc-supply = <&vmmcsd_fixed>;
343 bus-width = <8>;
344 non-removable;
345 status = "okay";
346};
347