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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm / nxp / imx / imx6dl-mamoj.dts
blob: 028951955bdee703ab42a56bf197292241df6b9c [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 BTicino
4 * Copyright (C) 2018 Amarula Solutions B.V.
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include "imx6dl.dtsi"
11
12/ {
13 model = "BTicino i.MX6DL Mamoj board";
14 compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
15
16 /* Will be filled by the bootloader */
17 memory@10000000 {
18 device_type = "memory";
19 reg = <0x10000000 0>;
20 };
21
22 backlight_lcd: backlight-lcd {
23 compatible = "pwm-backlight";
24 pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */
25 brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>;
26 default-brightness-level = <7>;
27 };
28
29 display: disp0 {
30 compatible = "fsl,imx-parallel-display";
31 #address-cells = <1>;
32 #size-cells = <0>;
33 interface-pix-fmt = "rgb24";
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_ipu1_lcdif>;
36 status = "okay";
37
38 port@0 {
39 reg = <0>;
40
41 lcd_display_in: endpoint {
42 remote-endpoint = <&ipu1_di0_disp0>;
43 };
44 };
45
46 port@1 {
47 reg = <1>;
48
49 lcd_display_out: endpoint {
50 remote-endpoint = <&lcd_panel_in>;
51 };
52 };
53 };
54
55 panel-lcd {
56 compatible = "rocktech,rk070er9427";
57 backlight = <&backlight_lcd>;
58 power-supply = <&reg_lcd_lr>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>;
61
62 port {
63 lcd_panel_in: endpoint {
64 remote-endpoint = <&lcd_display_out>;
65 };
66 };
67 };
68
69 reg_lcd_3v3: regulator-lcd-dvdd {
70 compatible = "regulator-fixed";
71 regulator-name = "lcd-dvdd";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 gpio = <&gpio3 1 0>;
75 enable-active-high;
76 startup-delay-us = <21000>;
77 };
78
79 reg_lcd_power: regulator-lcd-power {
80 compatible = "regulator-fixed";
81 regulator-name = "lcd-enable";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 gpio = <&gpio3 6 0>;
85 enable-active-high;
86 vin-supply = <&reg_lcd_3v3>;
87 };
88
89 reg_lcd_vgl: regulator-lcd-vgl {
90 compatible = "regulator-fixed";
91 regulator-name = "lcd-vgl";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
95 startup-delay-us = <6000>;
96 enable-active-high;
97 vin-supply = <&reg_lcd_power>;
98 };
99
100 reg_lcd_vgh: regulator-lcd-vgh {
101 compatible = "regulator-fixed";
102 regulator-name = "lcd-vgh";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
106 startup-delay-us = <6000>;
107 enable-active-high;
108 vin-supply = <&reg_lcd_avdd>;
109 };
110
111 reg_lcd_vcom: regulator-lcd-vcom {
112 compatible = "regulator-fixed";
113 regulator-name = "lcd-vcom";
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
116 gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>;
117 startup-delay-us = <11000>;
118 enable-active-high;
119 vin-supply = <&reg_lcd_vgh>;
120 };
121
122 reg_lcd_lr: regulator-lcd-lr {
123 compatible = "regulator-fixed";
124 regulator-name = "lcd-lr";
125 regulator-min-microvolt = <3300000>;
126 regulator-max-microvolt = <3300000>;
127 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
128 enable-active-high;
129 vin-supply = <&reg_lcd_vcom>;
130 };
131
132 reg_lcd_avdd: regulator-lcd-avdd {
133 compatible = "regulator-fixed";
134 regulator-name = "lcd-avdd";
135 regulator-min-microvolt = <10280000>;
136 regulator-max-microvolt = <10280000>;
137 gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
138 startup-delay-us = <6000>;
139 enable-active-high;
140 vin-supply = <&reg_lcd_vgl>;
141 };
142
143 reg_usb_host: regulator-usb-vbus {
144 compatible = "regulator-fixed";
145 regulator-name = "usbhost-vbus";
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_usbhost>;
148 regulator-min-microvolt = <50000000>;
149 regulator-max-microvolt = <50000000>;
150 gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>;
151 enable-active-high;
152 };
153
154 reg_wl18xx_vmmc: regulator-wl18xx-vmcc {
155 compatible = "regulator-fixed";
156 regulator-name = "vwl1807";
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_wlan>;
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
162 startup-delay-us = <70000>;
163 enable-active-high;
164 };
165};
166
167&fec {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_enet>;
170 phy-mode = "mii";
171 status = "okay";
172};
173
174&i2c3 {
175 clock-frequency = <400000>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_i2c3>;
178 status = "okay";
179};
180
181&i2c4 {
182 clock-frequency = <100000>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c4>;
185 status = "okay";
186
187 pfuze100: pmic@8 {
188 compatible = "fsl,pfuze100";
189 reg = <0x08>;
190
191 regulators {
192 /* CPU vdd_arm core */
193 sw1a_reg: sw1ab {
194 regulator-min-microvolt = <300000>;
195 regulator-max-microvolt = <1875000>;
196 regulator-boot-on;
197 regulator-always-on;
198 regulator-ramp-delay = <6250>;
199 };
200
201 /* SOC vdd_soc */
202 sw1c_reg: sw1c {
203 regulator-min-microvolt = <300000>;
204 regulator-max-microvolt = <1875000>;
205 regulator-boot-on;
206 regulator-always-on;
207 regulator-ramp-delay = <6250>;
208 };
209
210 /* I/O power GEN_3V3 */
211 sw2_reg: sw2 {
212 regulator-min-microvolt = <800000>;
213 regulator-max-microvolt = <3300000>;
214 regulator-boot-on;
215 regulator-always-on;
216 };
217
218 /* DDR memory */
219 sw3a_reg: sw3a {
220 regulator-min-microvolt = <400000>;
221 regulator-max-microvolt = <1975000>;
222 regulator-boot-on;
223 regulator-always-on;
224 };
225
226 /* DDR memory */
227 sw3b_reg: sw3b {
228 regulator-min-microvolt = <400000>;
229 regulator-max-microvolt = <1975000>;
230 regulator-boot-on;
231 regulator-always-on;
232 };
233
234 /* not used */
235 sw4_reg: sw4 {
236 regulator-min-microvolt = <800000>;
237 regulator-max-microvolt = <3300000>;
238 };
239
240 /* not used */
241 swbst_reg: swbst {
242 regulator-min-microvolt = <5000000>;
243 regulator-max-microvolt = <5150000>;
244 };
245
246 /* PMIC vsnvs. EX boot mode */
247 snvs_reg: vsnvs {
248 regulator-min-microvolt = <1000000>;
249 regulator-max-microvolt = <3000000>;
250 regulator-boot-on;
251 regulator-always-on;
252 };
253
254 vref_reg: vrefddr {
255 regulator-boot-on;
256 regulator-always-on;
257 };
258
259 /* not used */
260 vgen1_reg: vgen1 {
261 regulator-min-microvolt = <800000>;
262 regulator-max-microvolt = <1550000>;
263 };
264
265 /* not used */
266 vgen2_reg: vgen2 {
267 regulator-min-microvolt = <800000>;
268 regulator-max-microvolt = <1550000>;
269 };
270
271 /* not used */
272 vgen3_reg: vgen3 {
273 regulator-min-microvolt = <1800000>;
274 regulator-max-microvolt = <3300000>;
275 };
276
277 /* 1v8 general power */
278 vgen4_reg: vgen4 {
279 regulator-min-microvolt = <1800000>;
280 regulator-max-microvolt = <3300000>;
281 regulator-always-on;
282 };
283
284 /* 2v8 general power IMX6 */
285 vgen5_reg: vgen5 {
286 regulator-min-microvolt = <1800000>;
287 regulator-max-microvolt = <3300000>;
288 regulator-always-on;
289 };
290
291 /* 3v3 Ethernet */
292 vgen6_reg: vgen6 {
293 regulator-min-microvolt = <1800000>;
294 regulator-max-microvolt = <3300000>;
295 regulator-always-on;
296 };
297 };
298 };
299};
300
301&ipu1_di0_disp0 {
302 remote-endpoint = <&lcd_display_in>;
303};
304
305&pwm3 {
306 #pwm-cells = <2>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_pwm3>;
309 status = "okay";
310};
311
312&uart3 {
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_uart3>;
315 status = "okay";
316};
317
318&usbh1 {
319 vbus-supply = <&reg_usb_host>;
320 status = "okay";
321};
322
323&usbotg {
324 dr_mode = "peripheral";
325 status = "okay";
326};
327
328&usdhc1 {
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_usdhc1>;
331 bus-width = <4>;
332 vmmc-supply = <&reg_wl18xx_vmmc>;
333 no-1-8-v;
334 non-removable;
335 wakeup-source;
336 keep-power-in-suspend;
337 cap-power-off-card;
338 max-frequency = <25000000>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "okay";
342
343 wlcore: wlcore@2 {
344 compatible = "ti,wl1837";
345 reg = <2>;
346 interrupt-parent = <&gpio6>;
347 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
348 tcxo-clock-frequency = <26000000>;
349 };
350};
351
352&usdhc3 {
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_usdhc3>;
355 bus-width = <8>;
356 non-removable;
357 keep-power-in-suspend;
358 status = "okay";
359};
360
361&iomuxc {
362 pinctrl_enet: enetgrp {
363 fsl,pins = <
364 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
365 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
366 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1
367 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
368 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
369 MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
370 MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
371 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
372 MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
373 MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1
374 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
375 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
376 MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
377 MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
378 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
379 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
380 MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
381 MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
382 >;
383 };
384
385 pinctrl_i2c3: i2c3grp {
386 fsl,pins = <
387 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
388 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
389 >;
390 };
391
392 pinctrl_i2c4: i2c4grp {
393 fsl,pins = <
394 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
395 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
396 >;
397 };
398
399 pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */
400 fsl,pins = <
401 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */
402 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
403 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */
404 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */
405 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */
406 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
407 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
408 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
409 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
410 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
411 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
412 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
413 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
414 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
415 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
416 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
417 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
418 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
419 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
420 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
421 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
422 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
423 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
424 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
425 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
426 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
427 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
428 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
429 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
430 >;
431 };
432
433 pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp {
434 fsl,pins = <
435 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */
436 MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */
437 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */
438 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */
439 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */
440 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */
441 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */
442 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */
443 >;
444 };
445
446 pinctrl_pwm3: pwm3grp {
447 fsl,pins = <
448 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
449 >;
450 };
451
452 pinctrl_uart3: uart3grp {
453 fsl,pins = <
454 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
455 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
456 >;
457 };
458
459 pinctrl_usbhost: usbhostgrp {
460 fsl,pins = <
461 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
462 >;
463 };
464
465 pinctrl_usdhc1: usdhc1grp {
466 fsl,pins = <
467 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069
468 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079
469 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069
470 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069
471 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069
472 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069
473 >;
474 };
475
476 pinctrl_usdhc3: usdhc3grp {
477 fsl,pins = <
478 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
479 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
480 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
481 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
482 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
483 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
484 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
485 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
486 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
487 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
488 >;
489 };
490
491 pinctrl_wlan: wlangrp {
492 fsl,pins = <
493 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0
494 >;
495 };
496};