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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm / nxp / imx / imx53-qsb-common.dtsi
blob: d804404464737114f9677de8e55854de051ef8ce [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include "imx53.dtsi"
7
8/ {
9 chosen {
10 stdout-path = &uart1;
11 };
12
13 memory@70000000 {
14 device_type = "memory";
15 reg = <0x70000000 0x20000000>,
16 <0xb0000000 0x20000000>;
17 };
18
19 backlight_parallel: backlight-parallel {
20 compatible = "pwm-backlight";
21 pwms = <&pwm2 0 5000000 0>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <7>;
24 };
25
26 display0: disp0 {
27 compatible = "fsl,imx-parallel-display";
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp0>;
30
31 #address-cells = <1>;
32 #size-cells = <0>;
33 status = "disabled";
34
35 port@0 {
36 reg = <0>;
37
38 display0_in: endpoint {
39 remote-endpoint = <&ipu_di0_disp0>;
40 };
41 };
42
43 port@1 {
44 reg = <1>;
45
46 display_out: endpoint {
47 remote-endpoint = <&panel_in>;
48 };
49 };
50 };
51
52 gpio-keys {
53 compatible = "gpio-keys";
54
55 key-power {
56 label = "Power Button";
57 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
58 linux,code = <KEY_POWER>;
59 };
60
61 key-volume-up {
62 label = "Volume Up";
63 gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
64 linux,code = <KEY_VOLUMEUP>;
65 wakeup-source;
66 };
67
68 key-volume-down {
69 label = "Volume Down";
70 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
71 linux,code = <KEY_VOLUMEDOWN>;
72 wakeup-source;
73 };
74 };
75
76 leds {
77 compatible = "gpio-leds";
78 pinctrl-names = "default";
79 pinctrl-0 = <&led_pin_gpio7_7>;
80
81 led-user {
82 label = "Heartbeat";
83 gpios = <&gpio7 7 0>;
84 linux,default-trigger = "heartbeat";
85 };
86 };
87
88 panel {
89 compatible = "sii,43wvf1g";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_display_power>;
92 backlight = <&backlight_parallel>;
93 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
94
95 port {
96 panel_in: endpoint {
97 remote-endpoint = <&display_out>;
98 };
99 };
100 };
101
102 reg_3p2v: regulator-3p2v {
103 compatible = "regulator-fixed";
104 regulator-name = "3P2V";
105 regulator-min-microvolt = <3200000>;
106 regulator-max-microvolt = <3200000>;
107 regulator-always-on;
108 };
109
110 reg_usb_vbus: regulator-usb-vbus {
111 compatible = "regulator-fixed";
112 regulator-name = "usb_vbus";
113 regulator-min-microvolt = <5000000>;
114 regulator-max-microvolt = <5000000>;
115 gpio = <&gpio7 8 0>;
116 enable-active-high;
117 };
118
119 sound {
120 compatible = "fsl,imx53-qsb-sgtl5000",
121 "fsl,imx-audio-sgtl5000";
122 model = "imx53-qsb-sgtl5000";
123 ssi-controller = <&ssi2>;
124 audio-codec = <&sgtl5000>;
125 audio-routing =
126 "MIC_IN", "Mic Jack",
127 "Mic Jack", "Mic Bias",
128 "Headphone Jack", "HP_OUT";
129 mux-int-port = <2>;
130 mux-ext-port = <5>;
131 };
132};
133
134&cpu0 {
135 /* CPU rated to 1GHz, not 1.2GHz as per the default settings */
136 operating-points = <
137 /* kHz uV */
138 166666 850000
139 400000 900000
140 800000 1050000
141 1000000 1200000
142 >;
143};
144
145&esdhc1 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_esdhc1>;
148 cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
149 status = "okay";
150};
151
152&ipu_di0_disp0 {
153 remote-endpoint = <&display0_in>;
154};
155
156&ssi2 {
157 status = "okay";
158};
159
160&esdhc3 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_esdhc3>;
163 cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
164 wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
165 bus-width = <8>;
166 status = "okay";
167};
168
169&iomuxc {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_hog>;
172
173 imx53-qsb {
174 pinctrl_hog: hoggrp {
175 fsl,pins = <
176 MX53_PAD_GPIO_8__GPIO1_8 0x80000000
177 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
178 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
179 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
180 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
181 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
182 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
183 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
184 >;
185 };
186
187 led_pin_gpio7_7: led_gpio7_7 {
188 fsl,pins = <
189 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
190 >;
191 };
192
193 pinctrl_audmux: audmuxgrp {
194 fsl,pins = <
195 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
196 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
197 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
198 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
199 >;
200 };
201
202 pinctrl_codec: codecgrp {
203 fsl,pins = <
204 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
205 >;
206 };
207
208 pinctrl_display_power: displaypowergrp {
209 fsl,pins = <
210 MX53_PAD_EIM_D24__GPIO3_24 0x1e4
211 >;
212 };
213
214 pinctrl_esdhc1: esdhc1grp {
215 fsl,pins = <
216 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
217 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
218 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
219 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
220 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
221 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
222 MX53_PAD_EIM_DA13__GPIO3_13 0xe4
223 >;
224 };
225
226 pinctrl_esdhc3: esdhc3grp {
227 fsl,pins = <
228 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
229 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
230 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
231 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
232 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
233 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
234 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
235 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
236 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
237 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
238 >;
239 };
240
241 pinctrl_fec: fecgrp {
242 fsl,pins = <
243 MX53_PAD_FEC_MDC__FEC_MDC 0x4
244 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
245 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
246 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
247 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
248 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
249 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
250 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
251 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
252 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
253 >;
254 };
255
256 /* open drain */
257 pinctrl_i2c1: i2c1grp {
258 fsl,pins = <
259 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
260 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
261 >;
262 };
263
264 pinctrl_i2c2: i2c2grp {
265 fsl,pins = <
266 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
267 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
268 >;
269 };
270
271 pinctrl_ipu_disp0: ipudisp0grp {
272 fsl,pins = <
273 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
274 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
275 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
276 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
277 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
278 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
279 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
280 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
281 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
282 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
283 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
284 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
285 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
286 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
287 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
288 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
289 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
290 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
291 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
292 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
293 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
294 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
295 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
296 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
297 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
298 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
299 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
300 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
301 >;
302 };
303
304 pinctrl_pwm2: pwm2grp {
305 fsl,pins = <
306 MX53_PAD_GPIO_1__PWM2_PWMO 0x5
307 >;
308 };
309
310 pinctrl_vga_sync: vgasync-grp {
311 fsl,pins = <
312 /* VGA_HSYNC, VSYNC with max drive strength */
313 MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
314 MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
315 >;
316 };
317
318 pinctrl_uart1: uart1grp {
319 fsl,pins = <
320 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
321 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
322 >;
323 };
324 };
325};
326
327&tve {
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_vga_sync>;
330 ddc-i2c-bus = <&i2c2>;
331 fsl,tve-mode = "vga";
332 fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */
333 fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */
334 status = "okay";
335};
336
337&uart1 {
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_uart1>;
340 status = "okay";
341};
342
343&i2c2 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_i2c2>;
346 status = "okay";
347
348 sgtl5000: codec@a {
349 compatible = "fsl,sgtl5000";
350 reg = <0x0a>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_codec>;
353 #sound-dai-cells = <0>;
354 VDDA-supply = <&reg_3p2v>;
355 VDDIO-supply = <&reg_3p2v>;
356 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
357 };
358};
359
360&i2c1 {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_i2c1>;
363 status = "okay";
364
365 accelerometer: mma8450@1c {
366 compatible = "fsl,mma8450";
367 reg = <0x1c>;
368 };
369};
370
371&audmux {
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_audmux>;
374 status = "okay";
375};
376
377&fec {
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_fec>;
380 phy-mode = "rmii";
381 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
382 status = "okay";
383};
384
385&pwm2 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_pwm2>;
388 status = "okay";
389};
390
391&sata {
392 status = "okay";
393};
394
395&vpu {
396 status = "okay";
397};
398
399&usbh1 {
400 vbus-supply = <&reg_usb_vbus>;
401 phy_type = "utmi";
402 status = "okay";
403};
404
405&usbotg {
406 dr_mode = "peripheral";
407 status = "okay";
408};