Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // Copyright (C) 2021 YADRO |
| 3 | /dts-v1/; |
| 4 | |
| 5 | #include "aspeed-bmc-vegman.dtsi" |
| 6 | |
| 7 | / { |
| 8 | model = "YADRO VEGMAN N110 BMC"; |
| 9 | compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500"; |
| 10 | }; |
| 11 | |
| 12 | &gpio { |
| 13 | status = "okay"; |
| 14 | gpio-line-names = |
| 15 | /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", |
| 16 | /*B0-B7*/ "","","","","","","","", |
| 17 | /*C0-C7*/ "","","","","","","","", |
| 18 | /*D0-D7*/ "","","","","","","","", |
| 19 | /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", |
| 20 | /*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","", |
| 21 | /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", |
| 22 | /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", |
| 23 | /*I0-I7*/ "","","","","","","","", |
| 24 | /*J0-J7*/ "","","","","","","","", |
| 25 | /*K0-K7*/ "","","","","","","","", |
| 26 | /*L0-L7*/ "","","","","","","","", |
| 27 | /*M0-M7*/ "","","","","","","","", |
| 28 | /*N0-N7*/ "","","","","","","","", |
| 29 | /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", |
| 30 | /*P0-P7*/ "","","","","","","","", |
| 31 | /*Q0-Q7*/ "","","","","","","","", |
| 32 | /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", |
| 33 | /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", |
| 34 | /*T0-T7*/ "","","","","","","","", |
| 35 | /*U0-U7*/ "","","","","","","","", |
| 36 | /*V0-V7*/ "","","","","","","","", |
| 37 | /*W0-W7*/ "","","","","","","","", |
| 38 | /*X0-X7*/ "","","","","","","","", |
| 39 | /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", |
| 40 | /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", |
| 41 | /*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", |
| 42 | /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", |
| 43 | /*AC0-AC7*/ "","","","","","","",""; |
| 44 | }; |
| 45 | |
| 46 | &sgpio { |
| 47 | ngpios = <80>; |
| 48 | bus-frequency = <2000000>; |
| 49 | status = "okay"; |
| 50 | /* SGPIO lines. even: input, odd: output */ |
| 51 | gpio-line-names = |
| 52 | /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", |
| 53 | /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", |
| 54 | /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", |
| 55 | /*D0-D7*/ "","","","","","","","","","","","","","","","", |
| 56 | /*E0-E7*/ "","","","","","","","","","","","","","","","", |
| 57 | /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", |
| 58 | /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", |
| 59 | /*H0-H7*/ "","","","","","","","","","","","","","","","", |
| 60 | /*I0-I7*/ "","","","","","","","","","","","","","","","", |
| 61 | /*J0-J7*/ "","","","","","","","","","","","","","","",""; |
| 62 | }; |
| 63 | |
| 64 | &i2c11 { |
| 65 | /* SMB_BMC_MGMT_LVC3 */ |
| 66 | gpio@21 { |
| 67 | compatible = "nxp,pcal9535"; |
| 68 | reg = <0x21>; |
| 69 | gpio-controller; |
| 70 | #gpio-cells = <2>; |
| 71 | gpio-line-names = |
| 72 | /*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "", |
| 73 | /*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", ""; |
| 74 | }; |
| 75 | gpio@27 { |
| 76 | compatible = "nxp,pca9698"; |
| 77 | reg = <0x27>; |
| 78 | gpio-controller; |
| 79 | #gpio-cells = <2>; |
| 80 | gpio-line-names = |
| 81 | /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", |
| 82 | /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", |
| 83 | /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "", |
| 84 | /*IO3.0-3.7*/ "", "", "", "", "", "", "", "", |
| 85 | /*IO4.0-4.7*/ "", "", "", "", "", "", "", ""; |
| 86 | }; |
| 87 | }; |
| 88 | |
| 89 | &i2c13 { |
| 90 | /* SMB_PCIE2_STBY_LVC3 */ |
| 91 | i2c-mux@71 { |
| 92 | compatible = "nxp,pca9543"; |
| 93 | reg = <0x71>; |
| 94 | #address-cells = <1>; |
| 95 | #size-cells = <0>; |
| 96 | i2c-mux-idle-disconnect; |
| 97 | }; |
| 98 | i2c-mux@73 { |
| 99 | compatible = "nxp,pca9545"; |
| 100 | reg = <0x73>; |
| 101 | #address-cells = <1>; |
| 102 | #size-cells = <0>; |
| 103 | i2c-mux-idle-disconnect; |
| 104 | }; |
| 105 | }; |
| 106 | |
| 107 | &i2c2 { |
| 108 | /* SMB_PCIE_STBY_LVC3 */ |
| 109 | i2c-mux@71 { |
| 110 | compatible = "nxp,pca9545"; |
| 111 | reg = <0x71>; |
| 112 | #address-cells = <1>; |
| 113 | #size-cells = <0>; |
| 114 | i2c-mux-idle-disconnect; |
| 115 | }; |
| 116 | }; |
| 117 | |
| 118 | &pwm_tacho { |
| 119 | status = "okay"; |
| 120 | pinctrl-names = "default"; |
| 121 | pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default |
| 122 | &pinctrl_pwm2_default &pinctrl_pwm3_default |
| 123 | &pinctrl_pwm4_default &pinctrl_pwm5_default>; |
| 124 | |
| 125 | fan@0 { |
| 126 | reg = <0x00>; |
| 127 | aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>; |
| 128 | }; |
| 129 | fan@1 { |
| 130 | reg = <0x01>; |
| 131 | aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; |
| 132 | }; |
| 133 | fan@2 { |
| 134 | reg = <0x02>; |
| 135 | aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; |
| 136 | }; |
| 137 | fan@3 { |
| 138 | reg = <0x03>; |
| 139 | aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; |
| 140 | }; |
| 141 | fan@4 { |
| 142 | reg = <0x04>; |
| 143 | aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; |
| 144 | }; |
| 145 | fan@5 { |
| 146 | reg = <0x05>; |
| 147 | aspeed,fan-tach-ch = /bits/ 8 <0x05>; |
| 148 | }; |
| 149 | }; |