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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / Bindings / thermal / qcom-tsens.yaml
blob: 99d9c526c0b6b4a02ecabc322d6eda4c88069d06 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2# Copyright 2019 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: QCOM SoC Temperature Sensor (TSENS)
9
10maintainers:
11 - Amit Kucheria <amitk@kernel.org>
12
13description: |
14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15 three distinct major versions of the IP that is supported by a single driver.
16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17 everything before v1 when there was no versioning information.
18
19properties:
20 compatible:
21 oneOf:
22 - description: msm8960 TSENS based
23 items:
24 - enum:
25 - qcom,ipq8064-tsens
26 - qcom,msm8960-tsens
27
28 - description: v0.1 of TSENS
29 items:
30 - enum:
31 - qcom,mdm9607-tsens
32 - qcom,msm8226-tsens
33 - qcom,msm8909-tsens
34 - qcom,msm8916-tsens
35 - qcom,msm8939-tsens
36 - qcom,msm8974-tsens
37 - const: qcom,tsens-v0_1
38
39 - description: v1 of TSENS
40 items:
41 - enum:
42 - qcom,msm8956-tsens
43 - qcom,msm8976-tsens
44 - qcom,qcs404-tsens
45 - const: qcom,tsens-v1
46
47 - description: v2 of TSENS
48 items:
49 - enum:
50 - qcom,msm8953-tsens
51 - qcom,msm8996-tsens
52 - qcom,msm8998-tsens
53 - qcom,qcm2290-tsens
54 - qcom,sa8775p-tsens
55 - qcom,sc7180-tsens
56 - qcom,sc7280-tsens
57 - qcom,sc8180x-tsens
58 - qcom,sc8280xp-tsens
59 - qcom,sdm630-tsens
60 - qcom,sdm845-tsens
61 - qcom,sm6115-tsens
62 - qcom,sm6350-tsens
63 - qcom,sm6375-tsens
64 - qcom,sm8150-tsens
65 - qcom,sm8250-tsens
66 - qcom,sm8350-tsens
67 - qcom,sm8450-tsens
68 - qcom,sm8550-tsens
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]69 - qcom,sm8650-tsens
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]70 - const: qcom,tsens-v2
71
72 - description: v2 of TSENS with combined interrupt
73 enum:
74 - qcom,ipq8074-tsens
75
76 - description: v2 of TSENS with combined interrupt
77 items:
78 - enum:
79 - qcom,ipq9574-tsens
80 - const: qcom,ipq8074-tsens
81
82 reg:
83 items:
84 - description: TM registers
85 - description: SROT registers
86
87 interrupts:
88 minItems: 1
89 maxItems: 2
90
91 interrupt-names:
92 minItems: 1
93 maxItems: 2
94
95 nvmem-cells:
96 oneOf:
97 - minItems: 1
98 maxItems: 2
99 description:
100 Reference to an nvmem node for the calibration data
101 - minItems: 5
102 maxItems: 35
103 description: |
104 Reference to nvmem cells for the calibration mode, two calibration
105 bases and two cells per each sensor
106 # special case for msm8974 / apq8084
107 - maxItems: 51
108 description: |
109 Reference to nvmem cells for the calibration mode, two calibration
110 bases and two cells per each sensor, main and backup copies, plus use_backup cell
111
112 nvmem-cell-names:
113 oneOf:
114 - minItems: 1
115 items:
116 - const: calib
117 - enum:
118 - calib_backup
119 - calib_sel
120 - minItems: 5
121 items:
122 - const: mode
123 - const: base1
124 - const: base2
125 - pattern: '^s[0-9]+_p1$'
126 - pattern: '^s[0-9]+_p2$'
127 - pattern: '^s[0-9]+_p1$'
128 - pattern: '^s[0-9]+_p2$'
129 - pattern: '^s[0-9]+_p1$'
130 - pattern: '^s[0-9]+_p2$'
131 - pattern: '^s[0-9]+_p1$'
132 - pattern: '^s[0-9]+_p2$'
133 - pattern: '^s[0-9]+_p1$'
134 - pattern: '^s[0-9]+_p2$'
135 - pattern: '^s[0-9]+_p1$'
136 - pattern: '^s[0-9]+_p2$'
137 - pattern: '^s[0-9]+_p1$'
138 - pattern: '^s[0-9]+_p2$'
139 - pattern: '^s[0-9]+_p1$'
140 - pattern: '^s[0-9]+_p2$'
141 - pattern: '^s[0-9]+_p1$'
142 - pattern: '^s[0-9]+_p2$'
143 - pattern: '^s[0-9]+_p1$'
144 - pattern: '^s[0-9]+_p2$'
145 - pattern: '^s[0-9]+_p1$'
146 - pattern: '^s[0-9]+_p2$'
147 - pattern: '^s[0-9]+_p1$'
148 - pattern: '^s[0-9]+_p2$'
149 - pattern: '^s[0-9]+_p1$'
150 - pattern: '^s[0-9]+_p2$'
151 - pattern: '^s[0-9]+_p1$'
152 - pattern: '^s[0-9]+_p2$'
153 - pattern: '^s[0-9]+_p1$'
154 - pattern: '^s[0-9]+_p2$'
155 - pattern: '^s[0-9]+_p1$'
156 - pattern: '^s[0-9]+_p2$'
157 # special case for msm8974 / apq8084
158 - items:
159 - const: mode
160 - const: base1
161 - const: base2
162 - const: use_backup
163 - const: mode_backup
164 - const: base1_backup
165 - const: base2_backup
166 - const: s0_p1
167 - const: s0_p2
168 - const: s1_p1
169 - const: s1_p2
170 - const: s2_p1
171 - const: s2_p2
172 - const: s3_p1
173 - const: s3_p2
174 - const: s4_p1
175 - const: s4_p2
176 - const: s5_p1
177 - const: s5_p2
178 - const: s6_p1
179 - const: s6_p2
180 - const: s7_p1
181 - const: s7_p2
182 - const: s8_p1
183 - const: s8_p2
184 - const: s9_p1
185 - const: s9_p2
186 - const: s10_p1
187 - const: s10_p2
188 - const: s0_p1_backup
189 - const: s0_p2_backup
190 - const: s1_p1_backup
191 - const: s1_p2_backup
192 - const: s2_p1_backup
193 - const: s2_p2_backup
194 - const: s3_p1_backup
195 - const: s3_p2_backup
196 - const: s4_p1_backup
197 - const: s4_p2_backup
198 - const: s5_p1_backup
199 - const: s5_p2_backup
200 - const: s6_p1_backup
201 - const: s6_p2_backup
202 - const: s7_p1_backup
203 - const: s7_p2_backup
204 - const: s8_p1_backup
205 - const: s8_p2_backup
206 - const: s9_p1_backup
207 - const: s9_p2_backup
208 - const: s10_p1_backup
209 - const: s10_p2_backup
210
211 "#qcom,sensors":
212 description:
213 Number of sensors enabled on this platform
214 $ref: /schemas/types.yaml#/definitions/uint32
215 minimum: 1
216 maximum: 16
217
218 "#thermal-sensor-cells":
219 const: 1
220 description:
221 Number of cells required to uniquely identify the thermal sensors. Since
222 we have multiple sensors this is set to 1
223
224required:
225 - compatible
226 - interrupts
227 - interrupt-names
228 - "#thermal-sensor-cells"
229 - "#qcom,sensors"
230
231allOf:
232 - if:
233 properties:
234 compatible:
235 contains:
236 enum:
237 - qcom,ipq8064-tsens
238 - qcom,msm8960-tsens
239 - qcom,tsens-v0_1
240 - qcom,tsens-v1
241 then:
242 properties:
243 interrupts:
244 items:
245 - description: Combined interrupt if upper or lower threshold crossed
246 interrupt-names:
247 items:
248 - const: uplow
249
250 - if:
251 properties:
252 compatible:
253 contains:
254 const: qcom,tsens-v2
255 then:
256 properties:
257 interrupts:
258 items:
259 - description: Combined interrupt if upper or lower threshold crossed
260 - description: Interrupt if critical threshold crossed
261 interrupt-names:
262 items:
263 - const: uplow
264 - const: critical
265
266 - if:
267 properties:
268 compatible:
269 contains:
270 enum:
271 - qcom,ipq8074-tsens
272 then:
273 properties:
274 interrupts:
275 items:
276 - description: Combined interrupt if upper, lower or critical thresholds crossed
277 interrupt-names:
278 items:
279 - const: combined
280
281 - if:
282 properties:
283 compatible:
284 contains:
285 enum:
286 - qcom,ipq8074-tsens
287 - qcom,tsens-v0_1
288 - qcom,tsens-v1
289 - qcom,tsens-v2
290
291 then:
292 required:
293 - reg
294
295additionalProperties: false
296
297examples:
298 - |
299 #include <dt-bindings/interrupt-controller/arm-gic.h>
300 // Example msm9860 based SoC (ipq8064):
301 gcc: clock-controller {
302
303 /* ... */
304
305 tsens: thermal-sensor {
306 compatible = "qcom,ipq8064-tsens";
307
308 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
309 nvmem-cell-names = "calib", "calib_backup";
310 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
311 interrupt-names = "uplow";
312
313 #qcom,sensors = <11>;
314 #thermal-sensor-cells = <1>;
315 };
316 };
317
318 - |
319 #include <dt-bindings/interrupt-controller/arm-gic.h>
320 // Example 1 (new calbiration data: for pre v1 IP):
321 thermal-sensor@4a9000 {
322 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
323 reg = <0x4a9000 0x1000>, /* TM */
324 <0x4a8000 0x1000>; /* SROT */
325
326 nvmem-cells = <&tsens_mode>,
327 <&tsens_base1>, <&tsens_base2>,
328 <&tsens_s0_p1>, <&tsens_s0_p2>,
329 <&tsens_s1_p1>, <&tsens_s1_p2>,
330 <&tsens_s2_p1>, <&tsens_s2_p2>,
331 <&tsens_s4_p1>, <&tsens_s4_p2>,
332 <&tsens_s5_p1>, <&tsens_s5_p2>;
333 nvmem-cell-names = "mode",
334 "base1", "base2",
335 "s0_p1", "s0_p2",
336 "s1_p1", "s1_p2",
337 "s2_p1", "s2_p2",
338 "s4_p1", "s4_p2",
339 "s5_p1", "s5_p2";
340
341 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "uplow";
343
344 #qcom,sensors = <5>;
345 #thermal-sensor-cells = <1>;
346 };
347
348 - |
349 #include <dt-bindings/interrupt-controller/arm-gic.h>
350 // Example 1 (legacy: for pre v1 IP):
351 tsens1: thermal-sensor@4a9000 {
352 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
353 reg = <0x4a9000 0x1000>, /* TM */
354 <0x4a8000 0x1000>; /* SROT */
355
356 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
357 nvmem-cell-names = "calib", "calib_sel";
358
359 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "uplow";
361
362 #qcom,sensors = <5>;
363 #thermal-sensor-cells = <1>;
364 };
365
366 - |
367 #include <dt-bindings/interrupt-controller/arm-gic.h>
368 // Example 2 (for any platform containing v1 of the TSENS IP):
369 tsens2: thermal-sensor@4a9000 {
370 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
371 reg = <0x004a9000 0x1000>, /* TM */
372 <0x004a8000 0x1000>; /* SROT */
373
374 nvmem-cells = <&tsens_caldata>;
375 nvmem-cell-names = "calib";
376
377 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
378 interrupt-names = "uplow";
379
380 #qcom,sensors = <10>;
381 #thermal-sensor-cells = <1>;
382 };
383
384 - |
385 #include <dt-bindings/interrupt-controller/arm-gic.h>
386 // Example 3 (for any platform containing v2 of the TSENS IP):
387 tsens3: thermal-sensor@c263000 {
388 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
389 reg = <0xc263000 0x1ff>,
390 <0xc222000 0x1ff>;
391
392 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
394 interrupt-names = "uplow", "critical";
395
396 #qcom,sensors = <13>;
397 #thermal-sensor-cells = <1>;
398 };
399
400 - |
401 #include <dt-bindings/interrupt-controller/arm-gic.h>
402 // Example 4 (for any IPQ8074 based SoC-s):
403 tsens4: thermal-sensor@4a9000 {
404 compatible = "qcom,ipq8074-tsens";
405 reg = <0x4a9000 0x1000>,
406 <0x4a8000 0x1000>;
407
408 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-names = "combined";
410
411 #qcom,sensors = <16>;
412 #thermal-sensor-cells = <1>;
413 };
414...