| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Samsung SoC series UFS PHY |
| 8 | |
| 9 | maintainers: |
| 10 | - Alim Akhtar <alim.akhtar@samsung.com> |
| 11 | |
| 12 | properties: |
| 13 | "#phy-cells": |
| 14 | const: 0 |
| 15 | |
| 16 | compatible: |
| 17 | enum: |
| 18 | - samsung,exynos7-ufs-phy |
| 19 | - samsung,exynosautov9-ufs-phy |
| 20 | - tesla,fsd-ufs-phy |
| 21 | |
| 22 | reg: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | reg-names: |
| 26 | items: |
| 27 | - const: phy-pma |
| 28 | |
| 29 | clocks: |
| 30 | minItems: 1 |
| 31 | maxItems: 4 |
| 32 | |
| 33 | clock-names: |
| 34 | minItems: 1 |
| 35 | maxItems: 4 |
| 36 | |
| 37 | samsung,pmu-syscon: |
| 38 | $ref: /schemas/types.yaml#/definitions/phandle-array |
| 39 | maxItems: 1 |
| 40 | items: |
| 41 | minItems: 1 |
| 42 | items: |
| 43 | - description: phandle for PMU system controller interface, used to |
| 44 | control pmu registers bits for ufs m-phy |
| 45 | - description: offset of the pmu control register |
| 46 | description: |
| 47 | It can be phandle/offset pair. The second cell which can represent an |
| 48 | offset is optional. |
| 49 | |
| 50 | required: |
| 51 | - "#phy-cells" |
| 52 | - compatible |
| 53 | - reg |
| 54 | - reg-names |
| 55 | - clocks |
| 56 | - clock-names |
| 57 | - samsung,pmu-syscon |
| 58 | |
| 59 | allOf: |
| 60 | - if: |
| 61 | properties: |
| 62 | compatible: |
| 63 | contains: |
| 64 | const: samsung,exynos7-ufs-phy |
| 65 | |
| 66 | then: |
| 67 | properties: |
| 68 | clocks: |
| 69 | items: |
| 70 | - description: PLL reference clock |
| 71 | - description: symbol clock for input symbol (rx0-ch0 symbol clock) |
| 72 | - description: symbol clock for input symbol (rx1-ch1 symbol clock) |
| 73 | - description: symbol clock for output symbol (tx0 symbol clock) |
| 74 | |
| 75 | clock-names: |
| 76 | items: |
| 77 | - const: ref_clk |
| 78 | - const: rx1_symbol_clk |
| 79 | - const: rx0_symbol_clk |
| 80 | - const: tx0_symbol_clk |
| 81 | |
| 82 | else: |
| 83 | properties: |
| 84 | clocks: |
| 85 | items: |
| 86 | - description: PLL reference clock |
| 87 | |
| 88 | clock-names: |
| 89 | items: |
| 90 | - const: ref_clk |
| 91 | |
| 92 | additionalProperties: false |
| 93 | |
| 94 | examples: |
| 95 | - | |
| 96 | #include <dt-bindings/clock/exynos7-clk.h> |
| 97 | |
| 98 | ufs_phy: ufs-phy@15571800 { |
| 99 | compatible = "samsung,exynos7-ufs-phy"; |
| 100 | reg = <0x15571800 0x240>; |
| 101 | reg-names = "phy-pma"; |
| 102 | samsung,pmu-syscon = <&pmu_system_controller>; |
| 103 | #phy-cells = <0>; |
| 104 | clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, |
| 105 | <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, |
| 106 | <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, |
| 107 | <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; |
| 108 | clock-names = "ref_clk", "rx1_symbol_clk", |
| 109 | "rx0_symbol_clk", "tx0_symbol_clk"; |
| 110 | |
| 111 | }; |
| 112 | ... |