blob: 1a5a12adb72b37cc0b71409b039df7772f9124d3 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Amlogic G12A USB3 + PCIE Combo PHY
9
10maintainers:
11 - Neil Armstrong <neil.armstrong@linaro.org>
12
13properties:
14 compatible:
15 enum:
16 - amlogic,g12a-usb3-pcie-phy
17
18 reg:
19 maxItems: 1
20
21 clocks:
22 maxItems: 1
23
24 clock-names:
25 items:
26 - const: ref_clk
27
28 resets:
29 maxItems: 1
30
31 reset-names:
32 items:
33 - const: phy
34
35 "#phy-cells":
36 const: 1
37
38 phy-supply:
39 description:
40 Phandle to a regulator that provides power to the PHY. This
41 regulator will be managed during the PHY power on/off sequence.
42
43required:
44 - compatible
45 - reg
46 - clocks
47 - clock-names
48 - resets
49 - reset-names
50 - "#phy-cells"
51
52additionalProperties: false
53
54examples:
55 - |
56 phy@46000 {
57 compatible = "amlogic,g12a-usb3-pcie-phy";
58 reg = <0x46000 0x2000>;
59 clocks = <&ref_clk>;
60 clock-names = "ref_clk";
61 resets = <&phy_reset>;
62 reset-names = "phy";
63 #phy-cells = <1>;
64 };