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git01.mediatek.com / filogic / uboot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / Bindings / net / renesas,etheravb.yaml
blob: de7ba7f345a937789299f6c5f91b6f96b376a5fd [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/renesas,etheravb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Ethernet AVB
8
9maintainers:
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
11
12properties:
13 compatible:
14 oneOf:
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
21 - renesas,etheravb-r8a77470 # RZ/G1C
22 - renesas,etheravb-r8a7790 # R-Car H2
23 - renesas,etheravb-r8a7791 # R-Car M2-W
24 - renesas,etheravb-r8a7792 # R-Car V2H
25 - renesas,etheravb-r8a7793 # R-Car M2-N
26 - renesas,etheravb-r8a7794 # R-Car E2
27 - const: renesas,etheravb-rcar-gen2 # R-Car Gen2 and RZ/G1
28
29 - items:
30 - enum:
31 - renesas,etheravb-r8a774a1 # RZ/G2M
32 - renesas,etheravb-r8a774b1 # RZ/G2N
33 - renesas,etheravb-r8a774c0 # RZ/G2E
34 - renesas,etheravb-r8a774e1 # RZ/G2H
35 - renesas,etheravb-r8a7795 # R-Car H3
36 - renesas,etheravb-r8a7796 # R-Car M3-W
37 - renesas,etheravb-r8a77961 # R-Car M3-W+
38 - renesas,etheravb-r8a77965 # R-Car M3-N
39 - renesas,etheravb-r8a77970 # R-Car V3M
40 - renesas,etheravb-r8a77980 # R-Car V3H
41 - renesas,etheravb-r8a77990 # R-Car E3
42 - renesas,etheravb-r8a77995 # R-Car D3
43 - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
44
45 - items:
46 - enum:
47 - renesas,etheravb-r8a779a0 # R-Car V3U
48 - renesas,etheravb-r8a779g0 # R-Car V4H
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]49 - renesas,etheravb-r8a779h0 # R-Car V4M
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]50 - const: renesas,etheravb-rcar-gen4 # R-Car Gen4
51
52 - items:
53 - enum:
54 - renesas,etheravb-r9a09g011 # RZ/V2M
55 - const: renesas,etheravb-rzv2m # RZ/V2M compatible
56
57 - items:
58 - enum:
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]59 - renesas,r9a07g043-gbeth # RZ/G2UL and RZ/Five
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]60 - renesas,r9a07g044-gbeth # RZ/G2{L,LC}
61 - renesas,r9a07g054-gbeth # RZ/V2L
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]62 - renesas,r9a08g045-gbeth # RZ/G3S
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]63 - const: renesas,rzg2l-gbeth # RZ/{G2L,G2UL,V2L} family
64
65 reg: true
66
67 interrupts: true
68
69 interrupt-names: true
70
71 clocks: true
72
73 clock-names: true
74
75 iommus:
76 maxItems: 1
77
78 power-domains:
79 maxItems: 1
80
81 resets:
82 maxItems: 1
83
84 phy-mode: true
85
86 phy-handle: true
87
88 '#address-cells':
89 description: Number of address cells for the MDIO bus.
90 const: 1
91
92 '#size-cells':
93 description: Number of size cells on the MDIO bus.
94 const: 0
95
96 renesas,no-ether-link:
97 type: boolean
98 description:
99 Specify when a board does not provide a proper AVB_LINK signal.
100
101 renesas,ether-link-active-low:
102 type: boolean
103 description:
104 Specify when the AVB_LINK signal is active-low instead of normal
105 active-high.
106
107 rx-internal-delay-ps:
108 enum: [0, 1800]
109
110 tx-internal-delay-ps:
111 enum: [0, 2000]
112
113patternProperties:
114 "@[0-9a-f]$":
115 type: object
116
117required:
118 - compatible
119 - reg
120 - interrupts
121 - clocks
122 - power-domains
123 - resets
124 - phy-mode
125 - phy-handle
126 - '#address-cells'
127 - '#size-cells'
128
129allOf:
130 - $ref: ethernet-controller.yaml#
131
132 - if:
133 properties:
134 compatible:
135 contains:
136 enum:
137 - renesas,etheravb-rcar-gen2
138 - renesas,etheravb-r8a7795
139 - renesas,etheravb-r8a7796
140 - renesas,etheravb-r8a77961
141 - renesas,etheravb-r8a77965
142 then:
143 properties:
144 reg:
145 items:
146 - description: MAC register block
147 - description: Stream buffer
148 else:
149 properties:
150 reg:
151 items:
152 - description: MAC register block
153
154 - if:
155 properties:
156 compatible:
157 contains:
158 enum:
159 - renesas,etheravb-rcar-gen2
160 - renesas,rzg2l-gbeth
161 then:
162 properties:
163 interrupts:
164 minItems: 1
165 maxItems: 3
166 interrupt-names:
167 minItems: 1
168 items:
169 - const: mux
170 - const: fil
171 - const: arp_ns
172 rx-internal-delay-ps: false
173 else:
174 if:
175 properties:
176 compatible:
177 contains:
178 const: renesas,etheravb-rzv2m
179 then:
180 properties:
181 interrupts:
182 minItems: 29
183 maxItems: 29
184 interrupt-names:
185 items:
186 pattern: '^(ch(1?)[0-9])|ch20|ch21|dia|dib|err_a|err_b|mgmt_a|mgmt_b|line3$'
187 rx-internal-delay-ps: false
188 required:
189 - interrupt-names
190 else:
191 properties:
192 interrupts:
193 minItems: 25
194 maxItems: 25
195 interrupt-names:
196 items:
197 pattern: '^ch[0-9]+$'
198 required:
199 - interrupt-names
200 - rx-internal-delay-ps
201
202 - if:
203 properties:
204 compatible:
205 contains:
206 enum:
207 - renesas,etheravb-r8a774a1
208 - renesas,etheravb-r8a774b1
209 - renesas,etheravb-r8a774e1
210 - renesas,etheravb-r8a7795
211 - renesas,etheravb-r8a7796
212 - renesas,etheravb-r8a77961
213 - renesas,etheravb-r8a77965
214 - renesas,etheravb-r8a77970
215 - renesas,etheravb-r8a77980
216 - renesas,etheravb-rcar-gen4
217 then:
218 required:
219 - tx-internal-delay-ps
220 else:
221 properties:
222 tx-internal-delay-ps: false
223
224 - if:
225 properties:
226 compatible:
227 contains:
228 const: renesas,etheravb-r8a77995
229 then:
230 properties:
231 rx-internal-delay-ps:
232 const: 1800
233
234 - if:
235 properties:
236 compatible:
237 contains:
238 const: renesas,etheravb-r8a77980
239 then:
240 properties:
241 tx-internal-delay-ps:
242 const: 2000
243
244 - if:
245 properties:
246 compatible:
247 contains:
248 const: renesas,rzg2l-gbeth
249 then:
250 properties:
251 clocks:
252 items:
253 - description: Main clock
254 - description: Register access clock
255 - description: Reference clock for RGMII
256 clock-names:
257 items:
258 - const: axi
259 - const: chi
260 - const: refclk
261 else:
262 if:
263 properties:
264 compatible:
265 contains:
266 const: renesas,etheravb-rzv2m
267 then:
268 properties:
269 clocks:
270 items:
271 - description: Main clock
272 - description: Coherent Hub Interface clock
273 - description: gPTP reference clock
274 clock-names:
275 items:
276 - const: axi
277 - const: chi
278 - const: gptp
279 else:
280 properties:
281 clocks:
282 minItems: 1
283 items:
284 - description: AVB functional clock
285 - description: Optional TXC reference clock
286 clock-names:
287 minItems: 1
288 items:
289 - const: fck
290 - const: refclk
291
292additionalProperties: false
293
294examples:
295 - |
296 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
297 #include <dt-bindings/interrupt-controller/arm-gic.h>
298 #include <dt-bindings/power/r8a7795-sysc.h>
299 #include <dt-bindings/gpio/gpio.h>
300 aliases {
301 ethernet0 = &avb;
302 };
303
304 avb: ethernet@e6800000 {
305 compatible = "renesas,etheravb-r8a7795",
306 "renesas,etheravb-rcar-gen3";
307 reg = <0xe6800000 0x800>, <0xe6a00000 0x10000>;
308 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
333 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6",
334 "ch7", "ch8", "ch9", "ch10", "ch11", "ch12",
335 "ch13", "ch14", "ch15", "ch16", "ch17", "ch18",
336 "ch19", "ch20", "ch21", "ch22", "ch23", "ch24";
337 clocks = <&cpg CPG_MOD 812>;
338 clock-names = "fck";
339 iommus = <&ipmmu_ds0 16>;
340 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
341 resets = <&cpg 812>;
342 phy-mode = "rgmii";
343 phy-handle = <&phy0>;
344 rx-internal-delay-ps = <0>;
345 tx-internal-delay-ps = <2000>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348
349 phy0: ethernet-phy@0 {
350 compatible = "ethernet-phy-id0022.1622",
351 "ethernet-phy-ieee802.3-c22";
352 rxc-skew-ps = <1500>;
353 reg = <0>;
354 interrupt-parent = <&gpio2>;
355 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
356 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
357 };
358 };