Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Xilinx Video IP Pipeline (VIPP) |
| 2 | ------------------------------- |
| 3 | |
| 4 | General concept |
| 5 | --------------- |
| 6 | |
| 7 | Xilinx video IP pipeline processes video streams through one or more Xilinx |
| 8 | video IP cores. Each video IP core is represented as documented in video.txt |
| 9 | and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT |
| 10 | node of the VIPP represents as a top level node of the pipeline and defines |
| 11 | mappings between DMAs and the video IP cores. |
| 12 | |
| 13 | Required properties: |
| 14 | |
| 15 | - compatible: Must be "xlnx,video". |
| 16 | |
| 17 | - dmas, dma-names: List of one DMA specifier and identifier string (as defined |
| 18 | in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port |
| 19 | requires a DMA channel with the identifier string set to "port" followed by |
| 20 | the port index. |
| 21 | |
| 22 | - ports: Video port, using the DT bindings defined in ../video-interfaces.txt. |
| 23 | |
| 24 | Required port properties: |
| 25 | |
| 26 | - direction: should be either "input" or "output" depending on the direction |
| 27 | of stream. |
| 28 | |
| 29 | Example: |
| 30 | |
| 31 | video_cap { |
| 32 | compatible = "xlnx,video"; |
| 33 | dmas = <&vdma_1 1>, <&vdma_3 1>; |
| 34 | dma-names = "port0", "port1"; |
| 35 | |
| 36 | ports { |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <0>; |
| 39 | |
| 40 | port@0 { |
| 41 | reg = <0>; |
| 42 | direction = "input"; |
| 43 | vcap0_in0: endpoint { |
| 44 | remote-endpoint = <&scaler0_out>; |
| 45 | }; |
| 46 | }; |
| 47 | port@1 { |
| 48 | reg = <1>; |
| 49 | direction = "input"; |
| 50 | vcap0_in1: endpoint { |
| 51 | remote-endpoint = <&switch_out1>; |
| 52 | }; |
| 53 | }; |
| 54 | }; |
| 55 | }; |