Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Specifying interrupt information for devices |
| 2 | ============================================ |
| 3 | |
| 4 | 1) Interrupt client nodes |
| 5 | ------------------------- |
| 6 | |
| 7 | Nodes that describe devices which generate interrupts must contain an |
| 8 | "interrupts" property, an "interrupts-extended" property, or both. If both are |
| 9 | present, the latter should take precedence; the former may be provided simply |
| 10 | for compatibility with software that does not recognize the latter. These |
| 11 | properties contain a list of interrupt specifiers, one per output interrupt. The |
| 12 | format of the interrupt specifier is determined by the interrupt controller to |
| 13 | which the interrupts are routed; see section 2 below for details. |
| 14 | |
| 15 | Example: |
| 16 | interrupt-parent = <&intc1>; |
| 17 | interrupts = <5 0>, <6 0>; |
| 18 | |
| 19 | The "interrupt-parent" property is used to specify the controller to which |
| 20 | interrupts are routed and contains a single phandle referring to the interrupt |
| 21 | controller node. This property is inherited, so it may be specified in an |
| 22 | interrupt client node or in any of its parent nodes. Interrupts listed in the |
| 23 | "interrupts" property are always in reference to the node's interrupt parent. |
| 24 | |
| 25 | The "interrupts-extended" property is a special form; useful when a node needs |
| 26 | to reference multiple interrupt parents or a different interrupt parent than |
| 27 | the inherited one. Each entry in this property contains both the parent phandle |
| 28 | and the interrupt specifier. |
| 29 | |
| 30 | Example: |
| 31 | interrupts-extended = <&intc1 5 1>, <&intc2 1 0>; |
| 32 | |
| 33 | 2) Interrupt controller nodes |
| 34 | ----------------------------- |
| 35 | |
| 36 | A device is marked as an interrupt controller with the "interrupt-controller" |
| 37 | property. This is a empty, boolean property. An additional "#interrupt-cells" |
| 38 | property defines the number of cells needed to specify a single interrupt. |
| 39 | |
| 40 | It is the responsibility of the interrupt controller's binding to define the |
| 41 | length and format of the interrupt specifier. The following two variants are |
| 42 | commonly used: |
| 43 | |
| 44 | a) one cell |
| 45 | ----------- |
| 46 | The #interrupt-cells property is set to 1 and the single cell defines the |
| 47 | index of the interrupt within the controller. |
| 48 | |
| 49 | Example: |
| 50 | |
| 51 | vic: intc@10140000 { |
| 52 | compatible = "arm,versatile-vic"; |
| 53 | interrupt-controller; |
| 54 | #interrupt-cells = <1>; |
| 55 | reg = <0x10140000 0x1000>; |
| 56 | }; |
| 57 | |
| 58 | sic: intc@10003000 { |
| 59 | compatible = "arm,versatile-sic"; |
| 60 | interrupt-controller; |
| 61 | #interrupt-cells = <1>; |
| 62 | reg = <0x10003000 0x1000>; |
| 63 | interrupt-parent = <&vic>; |
| 64 | interrupts = <31>; /* Cascaded to vic */ |
| 65 | }; |
| 66 | |
| 67 | b) two cells |
| 68 | ------------ |
| 69 | The #interrupt-cells property is set to 2 and the first cell defines the |
| 70 | index of the interrupt within the controller, while the second cell is used |
| 71 | to specify any of the following flags: |
| 72 | - bits[3:0] trigger type and level flags |
| 73 | 1 = low-to-high edge triggered |
| 74 | 2 = high-to-low edge triggered |
| 75 | 4 = active high level-sensitive |
| 76 | 8 = active low level-sensitive |
| 77 | |
| 78 | Example: |
| 79 | |
| 80 | i2c@7000c000 { |
| 81 | gpioext: gpio-adnp@41 { |
| 82 | compatible = "ad,gpio-adnp"; |
| 83 | reg = <0x41>; |
| 84 | |
| 85 | interrupt-parent = <&gpio>; |
| 86 | interrupts = <160 1>; |
| 87 | |
| 88 | gpio-controller; |
| 89 | #gpio-cells = <1>; |
| 90 | |
| 91 | interrupt-controller; |
| 92 | #interrupt-cells = <2>; |
| 93 | |
| 94 | nr-gpios = <64>; |
| 95 | }; |
| 96 | |
| 97 | sx8634@2b { |
| 98 | compatible = "smtc,sx8634"; |
| 99 | reg = <0x2b>; |
| 100 | |
| 101 | interrupt-parent = <&gpioext>; |
| 102 | interrupts = <3 0x8>; |
| 103 | |
| 104 | #address-cells = <1>; |
| 105 | #size-cells = <0>; |
| 106 | |
| 107 | threshold = <0x40>; |
| 108 | sensitivity = <7>; |
| 109 | }; |
| 110 | }; |
| 111 | |
| 112 | 3) Interrupt wakeup parent |
| 113 | -------------------------- |
| 114 | |
| 115 | Some interrupt controllers in a SoC, are always powered on and have a select |
| 116 | interrupts routed to them, so that they can wakeup the SoC from suspend. These |
| 117 | interrupt controllers do not fall into the category of a parent interrupt |
| 118 | controller and can be specified by the "wakeup-parent" property and contain a |
| 119 | single phandle referring to the wakeup capable interrupt controller. |
| 120 | |
| 121 | Example: |
| 122 | wakeup-parent = <&pdc_intc>; |