| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/renesas,shmobile-lcdc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Renesas SH-Mobile LCD Controller (LCDC) |
| 8 | |
| 9 | maintainers: |
| 10 | - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| 11 | - Geert Uytterhoeven <geert+renesas@glider.be> |
| 12 | |
| 13 | properties: |
| 14 | compatible: |
| 15 | enum: |
| 16 | - renesas,r8a7740-lcdc # R-Mobile A1 |
| 17 | - renesas,sh73a0-lcdc # SH-Mobile AG5 |
| 18 | |
| 19 | reg: |
| 20 | maxItems: 1 |
| 21 | |
| 22 | interrupts: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | clocks: |
| 26 | minItems: 1 |
| 27 | maxItems: 5 |
| 28 | description: |
| 29 | Only the functional clock is mandatory. |
| 30 | Some of the optional clocks are model-dependent (e.g. "video" (a.k.a. |
| 31 | "vou" or "dv_clk") is available on R-Mobile A1 only). |
| 32 | |
| 33 | clock-names: |
| 34 | minItems: 1 |
| 35 | items: |
| 36 | - const: fck |
| 37 | - enum: [ media, lclk, hdmi, video ] |
| 38 | - enum: [ media, lclk, hdmi, video ] |
| 39 | - enum: [ media, lclk, hdmi, video ] |
| 40 | - enum: [ media, lclk, hdmi, video ] |
| 41 | |
| 42 | power-domains: |
| 43 | maxItems: 1 |
| 44 | |
| 45 | ports: |
| 46 | $ref: /schemas/graph.yaml#/properties/ports |
| 47 | |
| 48 | properties: |
| 49 | port@0: |
| 50 | $ref: /schemas/graph.yaml#/properties/port |
| 51 | description: LCD port (R-Mobile A1 and SH-Mobile AG5) |
| 52 | unevaluatedProperties: false |
| 53 | |
| 54 | port@1: |
| 55 | $ref: /schemas/graph.yaml#/properties/port |
| 56 | description: HDMI port (R-Mobile A1 LCDC1 and SH-Mobile AG5) |
| 57 | unevaluatedProperties: false |
| 58 | |
| 59 | port@2: |
| 60 | $ref: /schemas/graph.yaml#/properties/port |
| 61 | description: MIPI-DSI port (SH-Mobile AG5) |
| 62 | unevaluatedProperties: false |
| 63 | |
| 64 | required: |
| 65 | - port@0 |
| 66 | |
| 67 | unevaluatedProperties: false |
| 68 | |
| 69 | required: |
| 70 | - compatible |
| 71 | - reg |
| 72 | - interrupts |
| 73 | - clocks |
| 74 | - clock-names |
| 75 | - power-domains |
| 76 | - ports |
| 77 | |
| 78 | additionalProperties: false |
| 79 | |
| 80 | allOf: |
| 81 | - if: |
| 82 | properties: |
| 83 | compatible: |
| 84 | contains: |
| 85 | const: renesas,r8a7740-lcdc |
| 86 | then: |
| 87 | properties: |
| 88 | ports: |
| 89 | properties: |
| 90 | port@2: false |
| 91 | |
| 92 | - if: |
| 93 | properties: |
| 94 | compatible: |
| 95 | contains: |
| 96 | const: renesas,sh73a0-lcdc |
| 97 | then: |
| 98 | properties: |
| 99 | ports: |
| 100 | required: |
| 101 | - port@1 |
| 102 | - port@2 |
| 103 | |
| 104 | examples: |
| 105 | - | |
| 106 | #include <dt-bindings/clock/r8a7740-clock.h> |
| 107 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 108 | |
| 109 | lcd-controller@fe940000 { |
| 110 | compatible = "renesas,r8a7740-lcdc"; |
| 111 | reg = <0xfe940000 0x4000>; |
| 112 | interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
| 113 | clocks = <&mstp1_clks R8A7740_CLK_LCDC0>, |
| 114 | <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>, |
| 115 | <&vou_clk>; |
| 116 | clock-names = "fck", "media", "lclk", "video"; |
| 117 | power-domains = <&pd_a4lc>; |
| 118 | |
| 119 | ports { |
| 120 | #address-cells = <1>; |
| 121 | #size-cells = <0>; |
| 122 | |
| 123 | port@0 { |
| 124 | reg = <0>; |
| 125 | |
| 126 | lcdc0_rgb: endpoint { |
| 127 | }; |
| 128 | }; |
| 129 | }; |
| 130 | }; |