| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: MediaTek frequency hopping and spread spectrum clocking control |
| 8 | |
| 9 | maintainers: |
| 10 | - Edward-JW Yang <edward-jw.yang@mediatek.com> |
| 11 | |
| 12 | description: | |
| 13 | Frequency hopping control (FHCTL) is a piece of hardware that control |
| 14 | some PLLs to adopt "hopping" mechanism to adjust their frequency. |
| 15 | Spread spectrum clocking (SSC) is another function provided by this hardware. |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | enum: |
| 20 | - mediatek,mt6795-fhctl |
| 21 | - mediatek,mt8173-fhctl |
| 22 | - mediatek,mt8186-fhctl |
| 23 | - mediatek,mt8192-fhctl |
| 24 | - mediatek,mt8195-fhctl |
| 25 | |
| 26 | reg: |
| 27 | maxItems: 1 |
| 28 | |
| 29 | clocks: |
| 30 | description: Phandles of the PLL with FHCTL hardware capability. |
| 31 | minItems: 1 |
| 32 | maxItems: 30 |
| 33 | |
| 34 | mediatek,hopping-ssc-percent: |
| 35 | description: The percentage of spread spectrum clocking for one PLL. |
| 36 | minItems: 1 |
| 37 | maxItems: 30 |
| 38 | items: |
| 39 | default: 0 |
| 40 | minimum: 0 |
| 41 | maximum: 8 |
| 42 | |
| 43 | required: |
| 44 | - compatible |
| 45 | - reg |
| 46 | - clocks |
| 47 | |
| 48 | additionalProperties: false |
| 49 | |
| 50 | examples: |
| 51 | - | |
| 52 | #include <dt-bindings/clock/mt8186-clk.h> |
| 53 | fhctl: fhctl@1000ce00 { |
| 54 | compatible = "mediatek,mt8186-fhctl"; |
| 55 | reg = <0x1000ce00 0x200>; |
| 56 | clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; |
| 57 | mediatek,hopping-ssc-percent = <3>; |
| 58 | }; |