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git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm / nxp / imx / imx6ull-tarragon-common.dtsi
blob: 3fdece5bd31f9d00de384b911ca554b93bbc33b0 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0 OR MIT
2//
3// Copyright (C) 2023 chargebyte GmbH
4
5/dts-v1/;
6
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/leds/common.h>
9#include <dt-bindings/pwm/pwm.h>
10#include "imx6ull.dtsi"
11
12/ {
13 aliases {
14 mmc0 = &usdhc2; /* eMMC */
15 };
16
17 chosen {
18 stdout-path = &uart4;
19 };
20
21 memory@80000000 {
22 device_type = "memory";
23 reg = <0x80000000 0x20000000>;
24 };
25
26 emmc_pwrseq: emmc-pwrseq {
27 compatible = "mmc-pwrseq-emmc";
28 pinctrl-0 = <&pinctrl_emmc_rst>;
29 pinctrl-names = "default";
30 reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
31 };
32
33 reg_dcdc_3v3: regulator-dcdc-3v3 {
34 compatible = "regulator-fixed";
35 regulator-name = "dcdc-3v3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 regulator-boot-on;
39 regulator-always-on;
40 };
41
42 reg_1v8: regulator-1v8 {
43 compatible = "regulator-fixed";
44 regulator-name = "ldo-1v8";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 regulator-boot-on;
48 regulator-always-on;
49 };
50
51 leds {
52 compatible = "gpio-leds";
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_status_leds>;
55
56 led-1 {
57 function = LED_FUNCTION_BOOT;
58 color = <LED_COLOR_ID_GREEN>;
59 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
60 linux,default-trigger = "timer";
61 };
62
63 led-2 {
64 function = LED_FUNCTION_PROGRAMMING;
65 color = <LED_COLOR_ID_YELLOW>;
66 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
67 };
68
69 led-3 {
70 function = LED_FUNCTION_HEARTBEAT;
71 color = <LED_COLOR_ID_RED>;
72 gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
73 linux,default-trigger = "heartbeat";
74 };
75 };
76};
77
78&adc1 {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_adc_motor
81 &pinctrl_adc_cp
82 &pinctrl_adc_pp>;
83 vref-supply = <&vgen1_reg>;
84 status = "okay";
85};
86
87&cpu0 {
88 clock-frequency = <792000000>;
89};
90
91&ecspi2 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ecspi2>;
96 num-cs = <3>;
97 cs-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH
98 &gpio3 2 GPIO_ACTIVE_HIGH
99 &gpio3 4 GPIO_ACTIVE_HIGH>;
100};
101
102&ecspi4 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_ecspi4>;
107 num-cs = <1>;
108 cs-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
109};
110
111&fec1 {
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_enet1
114 &pinctrl_enet1_phy_rst
115 &pinctrl_enet_mdio>;
116 phy-supply = <&reg_dcdc_3v3>;
117 phy-mode = "rmii";
118 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
119 phy-reset-duration = <25>;
120 phy-handle = <&ethphy0>;
121
122 mdio {
123 #address-cells = <1>;
124 #size-cells = <0>;
125
126 ethphy0: ethernet-phy@0 {
127 compatible = "ethernet-phy-ieee802.3-c22";
128 reg = <0>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_enet1_phy_int>;
131 interrupt-parent = <&gpio2>;
132 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
133 interrupts-extended = <&gpio2 7 IRQ_TYPE_EDGE_FALLING>;
134 clocks = <&clks IMX6UL_CLK_ENET_REF>;
135 clock-names = "rmii-ref";
136 max-speed = <100>;
137 smsc,disable-energy-detect;
138 };
139 };
140};
141
142&gpio1 {
143 gpio-line-names = "", /* 0 */
144 "",
145 "",
146 "",
147 "",
148 "", /* 5 */
149 "",
150 "",
151 "",
152 "",
153 "", /* 10 */
154 "",
155 "",
156 "CP_INVERT",
157 "",
158 "", /* 15 */
159 "",
160 "",
161 "",
162 "MOTOR_1_FAULT_N",
163 "", /* 20 */
164 "",
165 "ROTARY_SWITCH_1_2_N",
166 "ROTARY_SWITCH_1_4_N",
167 "ROTARY_SWITCH_1_8_N",
168 "MOTOR_2_FAULT_N"; /* 25 */
169};
170
171&gpio3 {
172 gpio-line-names = "", /* 0 */
173 "",
174 "",
175 "",
176 "",
177 "", /* 5 */
178 "EXT_GPIO",
179 "MOTOR_1_DRIVER_IN1_N",
180 "MOTOR_1_DRIVER_IN2",
181 "MOTOR_2_DRIVER_IN1",
182 "STM32_BOOT0", /* 10 */
183 "STM32_RST_N",
184 "RELAY_1_ENABLE",
185 "RELAY_2_ENABLE",
186 "",
187 "", /* 15 */
188 "QCA700X_MAINS_BOOTLOADER_N",
189 "QCA700X_CP_RST_N",
190 "QCA700X_CP_BOOTLOADER_N",
191 "",
192 "DIGITAL_OUT_1", /* 20 */
193 "DIGITAL_OUT_2",
194 "DIGITAL_OUT_3",
195 "DIGITAL_OUT_4",
196 "DIGITAL_OUT_5",
197 "DIGITAL_OUT_6", /* 25 */
198 "ROTARY_SWITCH_2_8_N",
199 "ROTARY_SWITCH_2_4_N",
200 "ROTARY_SWITCH_2_2_N";
201};
202
203&gpio4 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_pmic>;
206
207 gpio-line-names = "", /* 0 */
208 "",
209 "",
210 "",
211 "",
212 "", /* 5 */
213 "",
214 "",
215 "",
216 "",
217 "", /* 10 */
218 "",
219 "",
220 "BOARD_VARIANT_1",
221 "BOARD_VARIANT_2",
222 "BOARD_VARIANT_0", /* 15 */
223 "BOARD_VARIANT_3",
224 "",
225 "ROTARY_SWITCH_2_1_N",
226 "",
227 "DIGITAL_IN_5", /* 20 */
228 "",
229 "",
230 "DIGITAL_IN_6",
231 "",
232 "DIGITAL_IN_1", /* 25 */
233 "DIGITAL_IN_2",
234 "DIGITAL_IN_4",
235 "DIGITAL_IN_3";
236
237 pmic-int-hog {
238 gpio-hog;
239 gpios = <19 0>;
240 input;
241 };
242};
243
244&gpio5 {
245 gpio-line-names = "ROTARY_SWITCH_1_1_N", /* 0 */
246 "",
247 "RELAY_2_SENSE",
248 "RELAY_1_SENSE",
249 "",
250 "", /* 5 */
251 "",
252 "QCA700X_MAINS_RST_N",
253 "MOTOR_2_DRIVER_IN2",
254 "",
255 "CP_POSITIVE_PEAK_RST", /* 10 */
256 "CP_NEGATIVE_PEAK_RST";
257};
258
259&i2c4 {
260 clock-frequency = <100000>;
261 pinctrl-names = "default", "gpio";
262 pinctrl-0 = <&pinctrl_i2c4>;
263 pinctrl-1 = <&pinctrl_i2c4_gpio>;
264 scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
265 sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
266 status = "okay";
267
268 pfuze3001: pmic@8 {
269 compatible = "fsl,pfuze3001";
270 reg = <0x08>;
271
272 regulators {
273 sw1_reg: sw1 {
274 regulator-name = "SW1";
275 regulator-min-microvolt = <700000>;
276 regulator-max-microvolt = <3300000>;
277 regulator-boot-on;
278 regulator-always-on;
279 };
280
281 sw2_reg: sw2 {
282 regulator-name = "SW2";
283 regulator-min-microvolt = <1500000>;
284 regulator-max-microvolt = <3300000>;
285 regulator-boot-on;
286 regulator-always-on;
287 };
288
289 sw3_reg: sw3 {
290 regulator-name = "SW3";
291 regulator-min-microvolt = <900000>;
292 regulator-max-microvolt = <1650000>;
293 regulator-boot-on;
294 regulator-always-on;
295 };
296
297 snvs_reg: vsnvs {
298 regulator-name = "VSNVS";
299 regulator-min-microvolt = <1000000>;
300 regulator-max-microvolt = <3000000>;
301 regulator-boot-on;
302 regulator-always-on;
303 };
304
305 vgen1_reg: vldo1 {
306 regulator-name = "VLDO1";
307 regulator-min-microvolt = <1800000>;
308 regulator-max-microvolt = <3300000>;
309 regulator-always-on;
310 };
311
312 vgen2_reg: vldo2 {
313 regulator-name = "VLDO2";
314 regulator-min-microvolt = <800000>;
315 regulator-max-microvolt = <1550000>;
316 regulator-always-on;
317 };
318
319 vgen3_reg: vccsd {
320 regulator-name = "VCCSD";
321 regulator-min-microvolt = <2850000>;
322 regulator-max-microvolt = <3300000>;
323 regulator-always-on;
324 };
325
326 vgen4_reg: v33 {
327 regulator-name = "V33";
328 regulator-min-microvolt = <2850000>;
329 regulator-max-microvolt = <3300000>;
330 regulator-always-on;
331 };
332
333 vgen5_reg: vldo3 {
334 regulator-name = "VLDO3";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <3300000>;
337 regulator-always-on;
338 };
339
340 vgen6_reg: vldo4 {
341 regulator-name = "VLDO4";
342 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <3300000>;
344 regulator-always-on;
345 };
346 };
347 };
348
349 onewire@18 {
350 compatible = "maxim,ds2484";
351 reg = <0x18>;
352 };
353
354 accelerometer@19 {
355 compatible = "st,iis328dq", "st,h3lis331dl-accel";
356 reg = <0x19>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_accelerometer_int1_snvs>;
359 vdd-supply = <&reg_dcdc_3v3>;
360 vddio-supply = <&reg_dcdc_3v3>;
361 st,drdy-int-pin = <1>;
362 interrupt-parent = <&gpio5>;
363 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
364 };
365};
366
367&iomuxc {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_board_var
370 &pinctrl_digital_input
371 &pinctrl_digital_output
372 &pinctrl_gpio_motor
373 &pinctrl_hog_pins
374 &pinctrl_rotary_switch1
375 &pinctrl_rotary_switch2>;
376
377 pinctrl_adc_cp: adc-cpgrp {
378 fsl,pins = <
379 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
380 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
381 >;
382 };
383
384 pinctrl_adc_motor: adc-motorgrp {
385 fsl,pins = <
386 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
387 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
388 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
389 >;
390 };
391
392 pinctrl_adc_pp: adc-ppgrp {
393 fsl,pins = <
394 MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xb0
395 >;
396 };
397
398 pinctrl_board_var: board-vargrp {
399 fsl,pins = <
400 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0xb0
401 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0xb0
402 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0xb0
403 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0
404 >;
405 };
406
407 pinctrl_digital_input: digital-inputgrp {
408 fsl,pins = <
409 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0xb0
410 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0xb0
411 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0xb0
412 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0xb0
413 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0xb0
414 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0xb0
415 >;
416 };
417
418 pinctrl_digital_output: digital-outputgrp {
419 fsl,pins = <
420 MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x400000b0
421 MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x400000b0
422 MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x400000b0
423 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x400000b0
424 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x400000b0
425 MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x400000b0
426 >;
427 };
428
429 pinctrl_ecspi2: ecspi2grp {
430 fsl,pins = <
431 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0
432 MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0xb0
433 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xb0
434 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x10b0
435 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x10b0
436 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x10b0
437 >;
438 };
439
440 pinctrl_ecspi4: ecspi4grp {
441 fsl,pins = <
442 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x10b0
443 MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x10b0
444 MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x10b0
445 MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x10b0
446 >;
447 };
448
449 pinctrl_emmc_rst: emmc-rstgrp {
450 fsl,pins = <
451 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x400010b0
452 >;
453 };
454
455 pinctrl_enet_mdio: enet-mdiogrp {
456 fsl,pins = <
457 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10b0
458 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10b0
459 >;
460 };
461
462 pinctrl_enet1_phy_int: enet1-phy-intgrp {
463 fsl,pins = <
464 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0
465 >;
466 };
467
468 pinctrl_enet1: enet1grp {
469 fsl,pins = <
470 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x100b0
471 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x100b0
472 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0
473 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
474 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0xb0
475 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0xb0
476 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0xb0
477 >;
478 };
479
480 pinctrl_ext_uart: ext-uartgrp {
481 fsl,pins = <
482 MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0xb0
483 MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0xb0
484 >;
485 };
486
487 pinctrl_fan_enable: fan-enablegrp {
488 fsl,pins = <
489 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x400000b0
490 >;
491 };
492
493 pinctrl_gpio_motor: gpio-motorgrp {
494 fsl,pins = <
495 MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x400000b0
496 MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x400000b0
497 MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x400000b0
498 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0xb0
499 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0xb0
500 >;
501 };
502
503 pinctrl_hog_pins: hog-pinsgrp {
504 fsl,pins = <
505 MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x400000b0
506 MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x400000b0
507 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x400070a0
508 MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x400000b0
509 MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x400000b0
510 >;
511 };
512
513 pinctrl_i2c4: i2c4grp {
514 fsl,pins = <
515 MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x400008b0
516 MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x400008b0
517 >;
518 };
519
520 pinctrl_i2c4_gpio: i2c4-gpiogrp {
521 fsl,pins = <
522 MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x400008b0
523 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x400008b0
524 >;
525 };
526
527 pinctrl_pmic: pmicgrp {
528 fsl,pins = <
529 MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x70b1
530 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0xb0
531 >;
532 };
533
534 pinctrl_pwm_cp: pinctrl-pwm-cpgrp {
535 fsl,pins = <
536 MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x60a0
537 >;
538 };
539
540 pinctrl_pwm_digital_input_ref: pwm-digital-input-refgrp {
541 fsl,pins = <
542 MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0xb0
543 >;
544 };
545
546 pinctrl_pwm_fan: pwm-fangrp {
547 fsl,pins = <
548 MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x60a0
549 >;
550 };
551
552 pinctrl_qca700x_cp_btld: qca700x-cp-btldgrp {
553 fsl,pins = <
554 MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x400000b0
555 >;
556 };
557
558 pinctrl_qca700x_cp_int: qca700x-cp-intgrp {
559 fsl,pins = <
560 MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x10b0
561 >;
562 };
563
564 pinctrl_qca700x_cp_rst: qca700x-cp-rstgrp {
565 fsl,pins = <
566 MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x400000b0
567 >;
568 };
569
570 pinctrl_qca700x_mains_btld: qca700x-mains-btldgrp {
571 fsl,pins = <
572 MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x400000b0
573 >;
574 };
575
576 pinctrl_rotary_switch1: rotary-switch1grp {
577 fsl,pins = <
578 MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0xb0
579 MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0xb0
580 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0xb0
581 >;
582 };
583
584 pinctrl_rotary_switch2: rotary-switch2grp {
585 fsl,pins = <
586 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0xb0
587 MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0xb0
588 MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0xb0
589 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0xb0
590 >;
591 };
592
593 pinctrl_rs485_1: rs485-1grp {
594 fsl,pins = <
595 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0xb0
596 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0xb0
597 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0xb0
598 >;
599 };
600
601 pinctrl_rs485_2: rs485-2grp {
602 fsl,pins = <
603 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0
604 MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x10b0
605 MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x10b0
606 >;
607 };
608
609 pinctrl_status_leds: status-ledsgrp {
610 fsl,pins = <
611 MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0xb0
612 MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0xb0
613 MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0xb0
614 >;
615 };
616
617 pinctrl_stm32: stm32grp {
618 fsl,pins = <
619 MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x10b0
620 MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x10b0
621 >;
622 };
623
624 pinctrl_uart4: uart4grp {
625 fsl,pins = <
626 MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0xb0
627 MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0xb0
628 >;
629 };
630
631 pinctrl_usb: usbgrp {
632 fsl,pins = <
633 MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x70b0
634 MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x70b0
635 >;
636 };
637
638 pinctrl_usb_pwr: usb-pwrgrp {
639 fsl,pins = <
640 MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0xb0
641 >;
642 };
643
644 pinctrl_usdhc2: usdhc2grp {
645 fsl,pins = <
646 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x7071
647 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x7071
648 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x7071
649 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x7071
650 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x7071
651 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x7071
652 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x7071
653 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x7071
654 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x7071
655 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x7071
656 >;
657 };
658
659 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
660 fsl,pins = <
661 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70b1
662 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70b1
663 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70b1
664 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70b1
665 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70b1
666 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70b1
667 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70b1
668 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70b1
669 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70b1
670 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70b1
671 >;
672 };
673
674 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
675 fsl,pins = <
676 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70f1
677 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70f1
678 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70f1
679 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70f1
680 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70f1
681 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70f1
682 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70f1
683 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70f1
684 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70f1
685 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70f1
686 >;
687 };
688
689 pinctrl_wdog2: wdoggrp {
690 fsl,pins = <
691 MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x10b0
692 >;
693 };
694};
695
696&iomuxc_snvs {
697 pinctrl-names = "default_snvs";
698 pinctrl-0 = <&pinctrl_cp_peak_snvs
699 &pinctrl_gpio_motor_snvs
700 &pinctrl_relay_sense_snvs
701 &pinctrl_rotary_switch1_snvs>;
702
703 pinctrl_accelerometer_int1_snvs: accelerometer-int1-snvsgrp {
704 fsl,pins = <
705 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x130a0
706 >;
707 };
708
709 pinctrl_cp_peak_snvs: cp-peak-snvsgrp {
710 fsl,pins = <
711 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x130a0
712 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
713 >;
714 };
715
716 pinctrl_enet1_phy_rst: enet1-phy-rstgrp {
717 fsl,pins = <
718 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x100a0
719 >;
720 };
721
722 pinctrl_fan_sense_snvs: fan-sense-snvsgrp {
723 fsl,pins = <
724 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x100a0
725 >;
726 };
727
728 pinctrl_gpio_motor_snvs: gpio-motor-snvsgrp {
729 fsl,pins = <
730 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0
731 >;
732 };
733
734 pinctrl_qca700x_mains_int: qca700x-mains-intgrp {
735 fsl,pins = <
736 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x130a0
737 >;
738 };
739
740 pinctrl_qca700x_mains_rst: qca700x-mains-rstgrp {
741 fsl,pins = <
742 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400100a0
743 >;
744 };
745
746 pinctrl_relay_sense_snvs: relay-sense-snvsgrp {
747 fsl,pins = <
748 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x100a0
749 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x100a0
750 >;
751 };
752
753 pinctrl_rotary_switch1_snvs: rotary-switch1-snvsgrp {
754 fsl,pins = <
755 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x110a0
756 >;
757 };
758};
759
760&pwm2 {
761 pinctrl-names = "default";
762 pinctrl-0 = <&pinctrl_pwm_digital_input_ref>;
763 status = "okay";
764};
765
766&pwm8 {
767 pinctrl-names = "default";
768 pinctrl-0 = <&pinctrl_pwm_cp>;
769 status = "okay";
770};
771
772&uart1 {
773 pinctrl-names = "default";
774 pinctrl-0 = <&pinctrl_rs485_1>;
775 status = "okay";
776};
777
778&uart4 {
779 pinctrl-names = "default";
780 pinctrl-0 = <&pinctrl_uart4>;
781 fsl,dte-mode;
782 status = "okay";
783};
784
785&uart5 {
786 pinctrl-names = "default";
787 pinctrl-0 = <&pinctrl_rs485_2>;
788};
789
790&uart6 {
791 pinctrl-names = "default";
792 pinctrl-0 = <&pinctrl_stm32>;
793 status = "okay";
794};
795
796&uart7 {
797 pinctrl-names = "default";
798 pinctrl-0 = <&pinctrl_ext_uart>;
799 status = "okay";
800};
801
802&usbotg1 {
803 pinctrl-names = "default";
804 pinctrl-0 = <&pinctrl_usb
805 &pinctrl_usb_pwr>;
806 dr_mode = "host";
807 power-active-high;
808 disable-over-current;
809 status = "okay";
810};
811
812&usbotg2 {
813 dr_mode = "host";
814 disable-over-current;
815 status = "okay";
816};
817
818&usbphy1 {
819 fsl,tx-cal-45-dn-ohms = <35>;
820 fsl,tx-cal-45-dp-ohms = <35>;
821};
822
823&usbphy2 {
824 fsl,tx-cal-45-dn-ohms = <35>;
825 fsl,tx-cal-45-dp-ohms = <35>;
826};
827
828&usdhc2 {
829 pinctrl-names = "default", "state_100mhz", "state_200mhz";
830 pinctrl-0 = <&pinctrl_usdhc2>;
831 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
832 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
833 vmmc-supply = <&sw2_reg>;
834 vqmmc-supply = <&reg_1v8>;
835 mmc-pwrseq = <&emmc_pwrseq>;
836 bus-width = <8>;
837 non-removable;
838 no-sd;
839 no-sdio;
840 status = "okay";
841};
842
843&wdog1 {
844 status = "disabled";
845};
846
847&wdog2 {
848 pinctrl-names = "default";
849 pinctrl-0 = <&pinctrl_wdog2>;
850 fsl,ext-reset-output;
851 status = "okay";
852};