Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 6b9f0102c277ef110118c41a173c453fc6fd2899 / . / arch / powerpc / include / asm / global_data.h
blob: 1620fba0143419baf8703bad874375cde2fd357b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]2/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +0200[diff] [blame]3 * (C) Copyright 2002-2010
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]5 */
6
7#ifndef __ASM_GBL_DATA_H
8#define __ASM_GBL_DATA_H
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]9
Peter Tyserbe34d1d2009-09-21 11:20:37 -0500[diff] [blame]10#include "config.h"
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]11#include "asm/types.h"
12
Simon Glass3ac47d72012-12-13 20:48:30 +0000[diff] [blame]13/* Architecture-specific global data */
14struct arch_global_data {
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]15#if defined(CONFIG_FSL_ESDHC)
16 u32 sdhc_clk;
Yangbo Lu0fa68762019-12-19 18:59:28 +0800[diff] [blame]17 u32 sdhc_per_clk;
Yangbo Lub124f8a2015-04-22 13:57:00 +0800[diff] [blame]18#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
19 u8 sdhc_adapter;
20#endif
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]21#endif
Christophe Leroyb3510fb2018-03-16 17:20:41 +0100[diff] [blame]22#if defined(CONFIG_MPC8xx)
Christophe Leroy069fa832017-07-06 10:23:22 +0200[diff] [blame]23 unsigned long brg_clk;
24#endif
Simon Glass34a194f2012-12-13 20:48:44 +0000[diff] [blame]25#if defined(CONFIG_CPM2)
Simon Glass44ea8512012-12-13 20:48:46 +0000[diff] [blame]26 /* There are many clocks on the MPC8260 - see page 9-5 */
27 unsigned long vco_out;
28 unsigned long cpm_clk;
29 unsigned long scc_clk;
Simon Glass34a194f2012-12-13 20:48:44 +0000[diff] [blame]30 unsigned long brg_clk;
31#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]32 /* TODO: sjg@chromium.org: Should these be unslgned long? */
Peter Tyser62e73982009-05-22 17:23:24 -0500[diff] [blame]33#if defined(CONFIG_MPC83xx)
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]34#ifdef CONFIG_CLK_MPC83XX
35 u32 core_clk;
36#else
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]37 /* There are other clocks in the MPC83XX */
38 u32 csb_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]39# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]40 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]41 u32 tsec1_clk;
42 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]43 u32 usbdr_clk;
Mario Sixb2e701c2019-01-21 09:17:24 +0100[diff] [blame]44# elif defined(CONFIG_ARCH_MPC8309)
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000[diff] [blame]45 u32 usbdr_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]46# endif
Mario Six0344f5e2019-01-21 09:17:27 +0100[diff] [blame]47# if defined(CONFIG_ARCH_MPC834X)
Scott Woodbeb638a2007-04-16 14:34:18 -0500[diff] [blame]48 u32 usbmph_clk;
Mario Six0344f5e2019-01-21 09:17:27 +0100[diff] [blame]49# endif /* CONFIG_ARCH_MPC834X */
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]50# if defined(CONFIG_ARCH_MPC8315)
Dave Liue0cfec82007-09-18 12:36:58 +0800[diff] [blame]51 u32 tdm_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]52# endif
Dave Liua46daea2006-11-03 19:33:44 -0600[diff] [blame]53 u32 core_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]54 u32 enc_clk;
55 u32 lbiu_clk;
56 u32 lclk_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]57# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]58 defined(CONFIG_ARCH_MPC837X)
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]59 u32 pciexp1_clk;
60 u32 pciexp2_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]61# endif
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]62# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]63 u32 sata_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]64# endif
Mario Six84eb4312019-01-21 09:17:28 +0100[diff] [blame]65# if defined(CONFIG_ARCH_MPC8360)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]66 u32 mem_sec_clk;
Mario Six84eb4312019-01-21 09:17:28 +0100[diff] [blame]67# endif /* CONFIG_ARCH_MPC8360 */
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]68#endif
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]69#endif
Simon Glassa8b57392012-12-13 20:48:48 +0000[diff] [blame]70#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
71 u32 lbc_clk;
72 void *cpu;
73#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
Simon Glassc2baaec2012-12-13 20:48:49 +0000[diff] [blame]74#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
75 defined(CONFIG_MPC86xx)
76 u32 i2c1_clk;
77 u32 i2c2_clk;
78#endif
Simon Glass8518b172012-12-13 20:48:50 +0000[diff] [blame]79#if defined(CONFIG_QE)
80 u32 qe_clk;
81 u32 brg_clk;
82 uint mp_alloc_base;
83 uint mp_alloc_top;
84#endif /* CONFIG_QE */
Simon Glassc6622d62012-12-13 20:48:51 +0000[diff] [blame]85#if defined(CONFIG_FSL_LAW)
86 u32 used_laws;
87#endif
Simon Glass0b466582012-12-13 20:48:52 +0000[diff] [blame]88#if defined(CONFIG_E500)
89 u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
90#endif
Simon Glass4d6eaa32012-12-13 20:48:56 +0000[diff] [blame]91 unsigned long reset_status; /* reset status register at boot */
Simon Glass387a1f22012-12-13 20:48:57 +0000[diff] [blame]92#if defined(CONFIG_MPC83xx)
93 unsigned long arbiter_event_attributes;
94 unsigned long arbiter_event_address;
95#endif
Simon Glass89370732017-01-23 13:31:23 -0700[diff] [blame]96#if defined(CONFIG_CPM2)
Simon Glass93980082012-12-13 20:48:58 +0000[diff] [blame]97 unsigned int dp_alloc_base;
98 unsigned int dp_alloc_top;
99#endif
Simon Glassf2d9aaf2012-12-13 20:49:02 +0000[diff] [blame]100#ifdef CONFIG_SYS_FPGA_COUNT
101 unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
102#endif
Stefan Roeseb47a63d2015-10-02 08:20:35 +0200[diff] [blame]103#if defined(CONFIG_WD_MAX_RATE)
104 unsigned long long wdt_last; /* trace watch-dog triggering rate */
105#endif
106#if defined(CONFIG_LWMON5)
107 unsigned long kbd_status;
108#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]109};
110
Simon Glass1c62cc22012-12-13 20:49:23 +0000[diff] [blame]111#include <asm-generic/global_data.h>
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]112
113#if 1
Wolfgang Denk69c09642008-02-14 22:43:22 +0100[diff] [blame]114#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]115#else /* We could use plain global data, but the resulting code is bigger */
116#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
117#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
118 gd_t *gd
119#endif
120
121#endif /* __ASM_GBL_DATA_H */