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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Eran Liberty9095d4a2005-07-28 10:08:46 -05002/*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Dave Liu5245ff52007-09-18 12:36:11 +08006 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
Eran Liberty9095d4a2005-07-28 10:08:46 -05007 */
8
Mario Six7cab1472018-08-06 10:23:36 +02009#ifndef CONFIG_CLK_MPC83XX
10
Eran Liberty9095d4a2005-07-28 10:08:46 -050011#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -070012#include <clock_legacy.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050013#include <mpc83xx.h>
Kim Phillipsd82b0772007-04-30 15:26:21 -050014#include <command.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070015#include <vsprintf.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050016#include <asm/processor.h>
17
Wolfgang Denk6405a152006-03-31 18:32:53 +020018DECLARE_GLOBAL_DATA_PTR;
19
Eran Liberty9095d4a2005-07-28 10:08:46 -050020/* ----------------------------------------------------------------- */
21
22typedef enum {
23 _unk,
24 _off,
25 _byp,
26 _x8,
27 _x4,
28 _x2,
29 _x1,
30 _1x,
31 _1_5x,
32 _2x,
33 _2_5x,
34 _3x
35} mult_t;
36
37typedef struct {
38 mult_t core_csb_ratio;
Kim Phillipsbae24792006-11-02 19:47:11 -060039 mult_t vco_divider;
Eran Liberty9095d4a2005-07-28 10:08:46 -050040} corecnf_t;
41
Kim Phillipsb5c312a2012-10-29 13:34:39 +000042static corecnf_t corecnf_tab[] = {
Kim Phillipsbae24792006-11-02 19:47:11 -060043 {_byp, _byp}, /* 0x00 */
44 {_byp, _byp}, /* 0x01 */
45 {_byp, _byp}, /* 0x02 */
46 {_byp, _byp}, /* 0x03 */
47 {_byp, _byp}, /* 0x04 */
48 {_byp, _byp}, /* 0x05 */
49 {_byp, _byp}, /* 0x06 */
50 {_byp, _byp}, /* 0x07 */
51 {_1x, _x2}, /* 0x08 */
52 {_1x, _x4}, /* 0x09 */
53 {_1x, _x8}, /* 0x0A */
54 {_1x, _x8}, /* 0x0B */
55 {_1_5x, _x2}, /* 0x0C */
56 {_1_5x, _x4}, /* 0x0D */
57 {_1_5x, _x8}, /* 0x0E */
58 {_1_5x, _x8}, /* 0x0F */
59 {_2x, _x2}, /* 0x10 */
60 {_2x, _x4}, /* 0x11 */
61 {_2x, _x8}, /* 0x12 */
62 {_2x, _x8}, /* 0x13 */
63 {_2_5x, _x2}, /* 0x14 */
64 {_2_5x, _x4}, /* 0x15 */
65 {_2_5x, _x8}, /* 0x16 */
66 {_2_5x, _x8}, /* 0x17 */
67 {_3x, _x2}, /* 0x18 */
68 {_3x, _x4}, /* 0x19 */
69 {_3x, _x8}, /* 0x1A */
70 {_3x, _x8}, /* 0x1B */
Eran Liberty9095d4a2005-07-28 10:08:46 -050071};
72
73/* ----------------------------------------------------------------- */
74
75/*
76 *
77 */
Kim Phillipsbae24792006-11-02 19:47:11 -060078int get_clocks(void)
Eran Liberty9095d4a2005-07-28 10:08:46 -050079{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Eran Liberty9095d4a2005-07-28 10:08:46 -050081 u32 pci_sync_in;
Kim Phillipsbae24792006-11-02 19:47:11 -060082 u8 spmf;
83 u8 clkin_div;
Eran Liberty9095d4a2005-07-28 10:08:46 -050084 u32 sccr;
85 u32 corecnf_tab_index;
Kim Phillipsbae24792006-11-02 19:47:11 -060086 u8 corepll;
Eran Liberty9095d4a2005-07-28 10:08:46 -050087 u32 lcrr;
Jon Loeligerebc72242005-08-01 13:20:47 -050088
Eran Liberty9095d4a2005-07-28 10:08:46 -050089 u32 csb_clk;
Mario Six9164bdd2019-01-21 09:17:25 +010090#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +010091 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Eran Liberty9095d4a2005-07-28 10:08:46 -050092 u32 tsec1_clk;
93 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050094 u32 usbdr_clk;
Mario Sixb2e701c2019-01-21 09:17:24 +010095#elif defined(CONFIG_ARCH_MPC8309)
Gerlando Falautofe201cb2012-10-10 22:13:08 +000096 u32 usbdr_clk;
Dave Liua46daea2006-11-03 19:33:44 -060097#endif
Mario Six0344f5e2019-01-21 09:17:27 +010098#ifdef CONFIG_ARCH_MPC834X
Scott Woodc036fc92007-04-16 14:34:19 -050099 u32 usbmph_clk;
100#endif
Dave Liua46daea2006-11-03 19:33:44 -0600101 u32 core_clk;
102 u32 i2c1_clk;
Mario Sixbe07e552019-01-21 09:17:26 +0100103#if !defined(CONFIG_ARCH_MPC832X)
Dave Liua46daea2006-11-03 19:33:44 -0600104 u32 i2c2_clk;
Dave Liue740c462006-12-07 21:13:15 +0800105#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100106#if defined(CONFIG_ARCH_MPC8315)
Dave Liue0cfec82007-09-18 12:36:58 +0800107 u32 tdm_clk;
108#endif
Rini van Zettena2496172010-04-15 16:03:05 +0200109#if defined(CONFIG_FSL_ESDHC)
Dave Liu5245ff52007-09-18 12:36:11 +0800110 u32 sdhc_clk;
111#endif
Mario Sixb2e701c2019-01-21 09:17:24 +0100112#if !defined(CONFIG_ARCH_MPC8309)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500113 u32 enc_clk;
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000114#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500115 u32 lbiu_clk;
116 u32 lclk_clk;
Kim Phillipsc02cf1e2008-03-28 10:18:40 -0500117 u32 mem_clk;
Mario Six84eb4312019-01-21 09:17:28 +0100118#if defined(CONFIG_ARCH_MPC8360)
Kim Phillipsc02cf1e2008-03-28 10:18:40 -0500119 u32 mem_sec_clk;
Dave Liue740c462006-12-07 21:13:15 +0800120#endif
Gerlando Falauto77cf2832012-10-10 22:13:06 +0000121#if defined(CONFIG_QE)
Dave Liua46daea2006-11-03 19:33:44 -0600122 u32 qepmf;
123 u32 qepdf;
Dave Liua46daea2006-11-03 19:33:44 -0600124 u32 qe_clk;
125 u32 brg_clk;
126#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100127#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100128 defined(CONFIG_ARCH_MPC837X)
Dave Liu5245ff52007-09-18 12:36:11 +0800129 u32 pciexp1_clk;
130 u32 pciexp2_clk;
Dave Liue0cfec82007-09-18 12:36:58 +0800131#endif
Mario Six60b11232019-01-21 09:17:29 +0100132#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
Dave Liu5245ff52007-09-18 12:36:11 +0800133 u32 sata_clk;
134#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500135
Kim Phillipsbae24792006-11-02 19:47:11 -0600136 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500137 return -1;
Jon Loeligerebc72242005-08-01 13:20:47 -0500138
Dave Liua46daea2006-11-03 19:33:44 -0600139 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
Marian Balakowicz513b4a12005-10-11 19:09:42 +0200140
Dave Liua46daea2006-11-03 19:33:44 -0600141 if (im->reset.rcwh & HRCWH_PCI_HOST) {
Mario Sixd10f3182019-01-21 09:17:53 +0100142#if defined(CONFIG_SYS_CLK_FREQ)
143 pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
Dave Liua46daea2006-11-03 19:33:44 -0600144#else
145 pci_sync_in = 0xDEADBEEF;
146#endif
147 } else {
148#if defined(CONFIG_83XX_PCICLK)
149 pci_sync_in = CONFIG_83XX_PCICLK;
150#else
151 pci_sync_in = 0xDEADBEEF;
152#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500153 }
Marian Balakowicz513b4a12005-10-11 19:09:42 +0200154
Joakim Tjernlundf2af1bb2011-01-27 16:30:54 +0100155 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
Dave Liua46daea2006-11-03 19:33:44 -0600156 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
Jon Loeligerebc72242005-08-01 13:20:47 -0500157
Eran Liberty9095d4a2005-07-28 10:08:46 -0500158 sccr = im->clk.sccr;
Dave Liua46daea2006-11-03 19:33:44 -0600159
Mario Six9164bdd2019-01-21 09:17:25 +0100160#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100161 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500162 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
163 case 0:
164 tsec1_clk = 0;
165 break;
166 case 1:
167 tsec1_clk = csb_clk;
168 break;
169 case 2:
170 tsec1_clk = csb_clk / 2;
171 break;
172 case 3:
173 tsec1_clk = csb_clk / 3;
174 break;
175 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500176 /* unknown SCCR_TSEC1CM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800177 return -2;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500178 }
Gerlando Falauto74735552012-10-10 22:13:07 +0000179#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500180
Mario Six9164bdd2019-01-21 09:17:25 +0100181#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100182 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Scott Woodc036fc92007-04-16 14:34:19 -0500183 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
184 case 0:
185 usbdr_clk = 0;
186 break;
187 case 1:
188 usbdr_clk = csb_clk;
189 break;
190 case 2:
191 usbdr_clk = csb_clk / 2;
192 break;
193 case 3:
194 usbdr_clk = csb_clk / 3;
195 break;
196 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500197 /* unknown SCCR_USBDRCM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800198 return -3;
Scott Woodc036fc92007-04-16 14:34:19 -0500199 }
200#endif
201
Mario Six9164bdd2019-01-21 09:17:25 +0100202#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
Mario Six60b11232019-01-21 09:17:29 +0100203 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500204 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
205 case 0:
206 tsec2_clk = 0;
207 break;
208 case 1:
209 tsec2_clk = csb_clk;
210 break;
211 case 2:
212 tsec2_clk = csb_clk / 2;
213 break;
214 case 3:
215 tsec2_clk = csb_clk / 3;
216 break;
217 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500218 /* unknown SCCR_TSEC2CM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800219 return -4;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500220 }
Mario Six9164bdd2019-01-21 09:17:25 +0100221#elif defined(CONFIG_ARCH_MPC8313)
Dave Liu5245ff52007-09-18 12:36:11 +0800222 tsec2_clk = tsec1_clk;
Jon Loeligerebc72242005-08-01 13:20:47 -0500223
Dave Liu5245ff52007-09-18 12:36:11 +0800224 if (!(sccr & SCCR_TSEC1ON))
225 tsec1_clk = 0;
226 if (!(sccr & SCCR_TSEC2ON))
227 tsec2_clk = 0;
228#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500229
Mario Six0344f5e2019-01-21 09:17:27 +0100230#if defined(CONFIG_ARCH_MPC834X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500231 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
232 case 0:
233 usbmph_clk = 0;
234 break;
235 case 1:
236 usbmph_clk = csb_clk;
237 break;
238 case 2:
239 usbmph_clk = csb_clk / 2;
240 break;
241 case 3:
242 usbmph_clk = csb_clk / 3;
243 break;
244 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500245 /* unknown SCCR_USBMPHCM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800246 return -5;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500247 }
248
Kim Phillipsbae24792006-11-02 19:47:11 -0600249 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
250 /* if USB MPH clock is not disabled and
251 * USB DR clock is not disabled then
252 * USB MPH & USB DR must have the same rate
253 */
Dave Liu5245ff52007-09-18 12:36:11 +0800254 return -6;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500255 }
Dave Liu5245ff52007-09-18 12:36:11 +0800256#endif
Mario Sixb2e701c2019-01-21 09:17:24 +0100257#if !defined(CONFIG_ARCH_MPC8309)
Dave Liu5245ff52007-09-18 12:36:11 +0800258 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
259 case 0:
260 enc_clk = 0;
261 break;
262 case 1:
263 enc_clk = csb_clk;
264 break;
265 case 2:
266 enc_clk = csb_clk / 2;
267 break;
268 case 3:
269 enc_clk = csb_clk / 3;
270 break;
271 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500272 /* unknown SCCR_ENCCM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800273 return -7;
274 }
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000275#endif
Scott Woodc036fc92007-04-16 14:34:19 -0500276
Rini van Zettena2496172010-04-15 16:03:05 +0200277#if defined(CONFIG_FSL_ESDHC)
Dave Liu5245ff52007-09-18 12:36:11 +0800278 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
279 case 0:
280 sdhc_clk = 0;
281 break;
282 case 1:
283 sdhc_clk = csb_clk;
284 break;
285 case 2:
286 sdhc_clk = csb_clk / 2;
287 break;
288 case 3:
289 sdhc_clk = csb_clk / 3;
290 break;
291 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500292 /* unknown SCCR_SDHCCM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800293 return -8;
294 }
Dave Liua46daea2006-11-03 19:33:44 -0600295#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100296#if defined(CONFIG_ARCH_MPC8315)
Dave Liue0cfec82007-09-18 12:36:58 +0800297 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
298 case 0:
299 tdm_clk = 0;
300 break;
301 case 1:
302 tdm_clk = csb_clk;
303 break;
304 case 2:
305 tdm_clk = csb_clk / 2;
306 break;
307 case 3:
308 tdm_clk = csb_clk / 3;
309 break;
310 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500311 /* unknown SCCR_TDMCM value */
Dave Liue0cfec82007-09-18 12:36:58 +0800312 return -8;
313 }
314#endif
Scott Woodc036fc92007-04-16 14:34:19 -0500315
Mario Six0344f5e2019-01-21 09:17:27 +0100316#if defined(CONFIG_ARCH_MPC834X)
Dave Liu5245ff52007-09-18 12:36:11 +0800317 i2c1_clk = tsec2_clk;
Mario Six84eb4312019-01-21 09:17:28 +0100318#elif defined(CONFIG_ARCH_MPC8360)
Dave Liua46daea2006-11-03 19:33:44 -0600319 i2c1_clk = csb_clk;
Mario Sixbe07e552019-01-21 09:17:26 +0100320#elif defined(CONFIG_ARCH_MPC832X)
Dave Liu5245ff52007-09-18 12:36:11 +0800321 i2c1_clk = enc_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100322#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
Dave Liu5245ff52007-09-18 12:36:11 +0800323 i2c1_clk = enc_clk;
Rini van Zettena2496172010-04-15 16:03:05 +0200324#elif defined(CONFIG_FSL_ESDHC)
Dave Liu5245ff52007-09-18 12:36:11 +0800325 i2c1_clk = sdhc_clk;
Mario Six60b11232019-01-21 09:17:29 +0100326#elif defined(CONFIG_ARCH_MPC837X)
Andre Schwarza76cc612011-04-14 14:57:40 +0200327 i2c1_clk = enc_clk;
Mario Sixb2e701c2019-01-21 09:17:24 +0100328#elif defined(CONFIG_ARCH_MPC8309)
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000329 i2c1_clk = csb_clk;
Dave Liua46daea2006-11-03 19:33:44 -0600330#endif
Mario Sixbe07e552019-01-21 09:17:26 +0100331#if !defined(CONFIG_ARCH_MPC832X)
Dave Liu5245ff52007-09-18 12:36:11 +0800332 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
Dave Liue740c462006-12-07 21:13:15 +0800333#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500334
Mario Six9164bdd2019-01-21 09:17:25 +0100335#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100336 defined(CONFIG_ARCH_MPC837X)
Dave Liu5245ff52007-09-18 12:36:11 +0800337 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
Dave Liua46daea2006-11-03 19:33:44 -0600338 case 0:
Dave Liu5245ff52007-09-18 12:36:11 +0800339 pciexp1_clk = 0;
Dave Liua46daea2006-11-03 19:33:44 -0600340 break;
341 case 1:
Dave Liu5245ff52007-09-18 12:36:11 +0800342 pciexp1_clk = csb_clk;
Dave Liua46daea2006-11-03 19:33:44 -0600343 break;
344 case 2:
Dave Liu5245ff52007-09-18 12:36:11 +0800345 pciexp1_clk = csb_clk / 2;
Dave Liua46daea2006-11-03 19:33:44 -0600346 break;
347 case 3:
Dave Liu5245ff52007-09-18 12:36:11 +0800348 pciexp1_clk = csb_clk / 3;
Dave Liua46daea2006-11-03 19:33:44 -0600349 break;
350 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500351 /* unknown SCCR_PCIEXP1CM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800352 return -9;
Dave Liua46daea2006-11-03 19:33:44 -0600353 }
Dave Liue740c462006-12-07 21:13:15 +0800354
Dave Liu5245ff52007-09-18 12:36:11 +0800355 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
356 case 0:
357 pciexp2_clk = 0;
358 break;
359 case 1:
360 pciexp2_clk = csb_clk;
361 break;
362 case 2:
363 pciexp2_clk = csb_clk / 2;
364 break;
365 case 3:
366 pciexp2_clk = csb_clk / 3;
367 break;
368 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500369 /* unknown SCCR_PCIEXP2CM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800370 return -10;
371 }
372#endif
373
Mario Six60b11232019-01-21 09:17:29 +0100374#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
Dave Liub7896ad2008-01-17 18:23:19 +0800375 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
376 case 0:
Dave Liu5245ff52007-09-18 12:36:11 +0800377 sata_clk = 0;
378 break;
Dave Liub7896ad2008-01-17 18:23:19 +0800379 case 1:
Dave Liu5245ff52007-09-18 12:36:11 +0800380 sata_clk = csb_clk;
381 break;
Dave Liub7896ad2008-01-17 18:23:19 +0800382 case 2:
Dave Liu5245ff52007-09-18 12:36:11 +0800383 sata_clk = csb_clk / 2;
384 break;
Dave Liub7896ad2008-01-17 18:23:19 +0800385 case 3:
Dave Liu5245ff52007-09-18 12:36:11 +0800386 sata_clk = csb_clk / 3;
387 break;
388 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500389 /* unknown SCCR_SATA1CM value */
Dave Liu5245ff52007-09-18 12:36:11 +0800390 return -11;
391 }
392#endif
393
Kim Phillipsbae24792006-11-02 19:47:11 -0600394 lbiu_clk = csb_clk *
Joakim Tjernlundf2af1bb2011-01-27 16:30:54 +0100395 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
Becky Bruce0d4cee12010-06-17 11:37:20 -0500396 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500397 switch (lcrr) {
398 case 2:
399 case 4:
400 case 8:
401 lclk_clk = lbiu_clk / lcrr;
402 break;
403 default:
404 /* unknown lcrr */
Dave Liu5245ff52007-09-18 12:36:11 +0800405 return -12;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500406 }
Dave Liue740c462006-12-07 21:13:15 +0800407
Kim Phillipsc02cf1e2008-03-28 10:18:40 -0500408 mem_clk = csb_clk *
Joakim Tjernlundf2af1bb2011-01-27 16:30:54 +0100409 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
410 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
411
Mario Six84eb4312019-01-21 09:17:28 +0100412#if defined(CONFIG_ARCH_MPC8360)
Kim Phillipsc02cf1e2008-03-28 10:18:40 -0500413 mem_sec_clk = csb_clk * (1 +
Joakim Tjernlundf2af1bb2011-01-27 16:30:54 +0100414 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
Dave Liua46daea2006-11-03 19:33:44 -0600415#endif
Dave Liua46daea2006-11-03 19:33:44 -0600416
Eran Liberty9095d4a2005-07-28 10:08:46 -0500417 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
Robert P. J. Day0c911592016-05-23 06:49:21 -0400418 if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500419 /* corecnf_tab_index is too high, possibly wrong value */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500420 return -11;
421 }
422 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
423 case _byp:
424 case _x1:
425 case _1x:
426 core_clk = csb_clk;
427 break;
428 case _1_5x:
429 core_clk = (3 * csb_clk) / 2;
430 break;
431 case _2x:
432 core_clk = 2 * csb_clk;
433 break;
434 case _2_5x:
Kim Phillipsbae24792006-11-02 19:47:11 -0600435 core_clk = (5 * csb_clk) / 2;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500436 break;
437 case _3x:
438 core_clk = 3 * csb_clk;
439 break;
440 default:
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500441 /* unknown core to csb ratio */
Dave Liu5245ff52007-09-18 12:36:11 +0800442 return -13;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500443 }
Jon Loeligerebc72242005-08-01 13:20:47 -0500444
Gerlando Falauto77cf2832012-10-10 22:13:06 +0000445#if defined(CONFIG_QE)
Joakim Tjernlundf2af1bb2011-01-27 16:30:54 +0100446 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
447 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
Kim Phillipsbae24792006-11-02 19:47:11 -0600448 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
Dave Liua46daea2006-11-03 19:33:44 -0600449 brg_clk = qe_clk / 2;
450#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500451
Simon Glasscc76e9e2012-12-13 20:48:47 +0000452 gd->arch.csb_clk = csb_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100453#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100454 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000455 gd->arch.tsec1_clk = tsec1_clk;
456 gd->arch.tsec2_clk = tsec2_clk;
457 gd->arch.usbdr_clk = usbdr_clk;
Mario Sixb2e701c2019-01-21 09:17:24 +0100458#elif defined(CONFIG_ARCH_MPC8309)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000459 gd->arch.usbdr_clk = usbdr_clk;
Dave Liua46daea2006-11-03 19:33:44 -0600460#endif
Mario Six0344f5e2019-01-21 09:17:27 +0100461#if defined(CONFIG_ARCH_MPC834X)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000462 gd->arch.usbmph_clk = usbmph_clk;
Scott Woodc036fc92007-04-16 14:34:19 -0500463#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100464#if defined(CONFIG_ARCH_MPC8315)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000465 gd->arch.tdm_clk = tdm_clk;
Dave Liue0cfec82007-09-18 12:36:58 +0800466#endif
Rini van Zettena2496172010-04-15 16:03:05 +0200467#if defined(CONFIG_FSL_ESDHC)
Simon Glass9e247d12012-12-13 20:49:05 +0000468 gd->arch.sdhc_clk = sdhc_clk;
Dave Liu5245ff52007-09-18 12:36:11 +0800469#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000470 gd->arch.core_clk = core_clk;
Simon Glassc2baaec2012-12-13 20:48:49 +0000471 gd->arch.i2c1_clk = i2c1_clk;
Mario Sixbe07e552019-01-21 09:17:26 +0100472#if !defined(CONFIG_ARCH_MPC832X)
Simon Glassc2baaec2012-12-13 20:48:49 +0000473 gd->arch.i2c2_clk = i2c2_clk;
Dave Liue740c462006-12-07 21:13:15 +0800474#endif
Mario Sixb2e701c2019-01-21 09:17:24 +0100475#if !defined(CONFIG_ARCH_MPC8309)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000476 gd->arch.enc_clk = enc_clk;
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000477#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000478 gd->arch.lbiu_clk = lbiu_clk;
479 gd->arch.lclk_clk = lclk_clk;
Kim Phillipsc02cf1e2008-03-28 10:18:40 -0500480 gd->mem_clk = mem_clk;
Mario Six84eb4312019-01-21 09:17:28 +0100481#if defined(CONFIG_ARCH_MPC8360)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000482 gd->arch.mem_sec_clk = mem_sec_clk;
Dave Liue740c462006-12-07 21:13:15 +0800483#endif
Gerlando Falauto77cf2832012-10-10 22:13:06 +0000484#if defined(CONFIG_QE)
Simon Glass8518b172012-12-13 20:48:50 +0000485 gd->arch.qe_clk = qe_clk;
Simon Glass34a194f2012-12-13 20:48:44 +0000486 gd->arch.brg_clk = brg_clk;
Dave Liua46daea2006-11-03 19:33:44 -0600487#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100488#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100489 defined(CONFIG_ARCH_MPC837X)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000490 gd->arch.pciexp1_clk = pciexp1_clk;
491 gd->arch.pciexp2_clk = pciexp2_clk;
Dave Liue0cfec82007-09-18 12:36:58 +0800492#endif
Mario Six60b11232019-01-21 09:17:29 +0100493#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000494 gd->arch.sata_clk = sata_clk;
Dave Liu5245ff52007-09-18 12:36:11 +0800495#endif
Kim Phillipscd9fd702007-08-15 22:30:19 -0500496 gd->pci_clk = pci_sync_in;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000497 gd->cpu_clk = gd->arch.core_clk;
498 gd->bus_clk = gd->arch.csb_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500499 return 0;
Dave Liua46daea2006-11-03 19:33:44 -0600500
Eran Liberty9095d4a2005-07-28 10:08:46 -0500501}
502
503/********************************************
504 * get_bus_freq
505 * return system bus freq in Hz
506 *********************************************/
Kim Phillipsbae24792006-11-02 19:47:11 -0600507ulong get_bus_freq(ulong dummy)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500508{
Simon Glasscc76e9e2012-12-13 20:48:47 +0000509 return gd->arch.csb_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500510}
511
York Sune12ce982011-08-26 11:32:44 -0700512/********************************************
513 * get_ddr_freq
514 * return ddr bus freq in Hz
515 *********************************************/
516ulong get_ddr_freq(ulong dummy)
517{
518 return gd->mem_clk;
519}
520
Mario Six2fc52272019-01-21 09:18:05 +0100521int get_serial_clock(void)
522{
523 return get_bus_freq(0);
524}
525
Simon Glassed38aef2020-05-10 11:40:03 -0600526static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
527 char *const argv[])
Eran Liberty9095d4a2005-07-28 10:08:46 -0500528{
Wolfgang Denk20591042008-10-19 02:35:49 +0200529 char buf[32];
530
Eran Liberty9095d4a2005-07-28 10:08:46 -0500531 printf("Clock configuration:\n");
Simon Glasscc76e9e2012-12-13 20:48:47 +0000532 printf(" Core: %-4s MHz\n",
533 strmhz(buf, gd->arch.core_clk));
534 printf(" Coherent System Bus: %-4s MHz\n",
535 strmhz(buf, gd->arch.csb_clk));
Gerlando Falauto77cf2832012-10-10 22:13:06 +0000536#if defined(CONFIG_QE)
Simon Glass8518b172012-12-13 20:48:50 +0000537 printf(" QE: %-4s MHz\n",
538 strmhz(buf, gd->arch.qe_clk));
Simon Glass34a194f2012-12-13 20:48:44 +0000539 printf(" BRG: %-4s MHz\n",
540 strmhz(buf, gd->arch.brg_clk));
Dave Liua46daea2006-11-03 19:33:44 -0600541#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000542 printf(" Local Bus Controller:%-4s MHz\n",
543 strmhz(buf, gd->arch.lbiu_clk));
544 printf(" Local Bus: %-4s MHz\n",
545 strmhz(buf, gd->arch.lclk_clk));
Wolfgang Denk20591042008-10-19 02:35:49 +0200546 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
Mario Six84eb4312019-01-21 09:17:28 +0100547#if defined(CONFIG_ARCH_MPC8360)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000548 printf(" DDR Secondary: %-4s MHz\n",
549 strmhz(buf, gd->arch.mem_sec_clk));
Dave Liua46daea2006-11-03 19:33:44 -0600550#endif
Mario Sixb2e701c2019-01-21 09:17:24 +0100551#if !defined(CONFIG_ARCH_MPC8309)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000552 printf(" SEC: %-4s MHz\n",
553 strmhz(buf, gd->arch.enc_clk));
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000554#endif
Simon Glassc2baaec2012-12-13 20:48:49 +0000555 printf(" I2C1: %-4s MHz\n",
556 strmhz(buf, gd->arch.i2c1_clk));
Mario Sixbe07e552019-01-21 09:17:26 +0100557#if !defined(CONFIG_ARCH_MPC832X)
Simon Glassc2baaec2012-12-13 20:48:49 +0000558 printf(" I2C2: %-4s MHz\n",
559 strmhz(buf, gd->arch.i2c2_clk));
Dave Liue740c462006-12-07 21:13:15 +0800560#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100561#if defined(CONFIG_ARCH_MPC8315)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000562 printf(" TDM: %-4s MHz\n",
563 strmhz(buf, gd->arch.tdm_clk));
Dave Liue0cfec82007-09-18 12:36:58 +0800564#endif
Rini van Zettena2496172010-04-15 16:03:05 +0200565#if defined(CONFIG_FSL_ESDHC)
Simon Glass9e247d12012-12-13 20:49:05 +0000566 printf(" SDHC: %-4s MHz\n",
567 strmhz(buf, gd->arch.sdhc_clk));
Dave Liu5245ff52007-09-18 12:36:11 +0800568#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100569#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100570 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000571 printf(" TSEC1: %-4s MHz\n",
572 strmhz(buf, gd->arch.tsec1_clk));
573 printf(" TSEC2: %-4s MHz\n",
574 strmhz(buf, gd->arch.tsec2_clk));
575 printf(" USB DR: %-4s MHz\n",
576 strmhz(buf, gd->arch.usbdr_clk));
Mario Sixb2e701c2019-01-21 09:17:24 +0100577#elif defined(CONFIG_ARCH_MPC8309)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000578 printf(" USB DR: %-4s MHz\n",
579 strmhz(buf, gd->arch.usbdr_clk));
Dave Liua46daea2006-11-03 19:33:44 -0600580#endif
Mario Six0344f5e2019-01-21 09:17:27 +0100581#if defined(CONFIG_ARCH_MPC834X)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000582 printf(" USB MPH: %-4s MHz\n",
583 strmhz(buf, gd->arch.usbmph_clk));
Scott Woodc036fc92007-04-16 14:34:19 -0500584#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100585#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100586 defined(CONFIG_ARCH_MPC837X)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000587 printf(" PCIEXP1: %-4s MHz\n",
588 strmhz(buf, gd->arch.pciexp1_clk));
589 printf(" PCIEXP2: %-4s MHz\n",
590 strmhz(buf, gd->arch.pciexp2_clk));
Dave Liue0cfec82007-09-18 12:36:58 +0800591#endif
Mario Six60b11232019-01-21 09:17:29 +0100592#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000593 printf(" SATA: %-4s MHz\n",
594 strmhz(buf, gd->arch.sata_clk));
Dave Liu5245ff52007-09-18 12:36:11 +0800595#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500596 return 0;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500597}
Kim Phillipsd82b0772007-04-30 15:26:21 -0500598
599U_BOOT_CMD(clocks, 1, 0, do_clocks,
Peter Tyserdfb72b82009-01-27 18:03:12 -0600600 "print clock configuration",
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200601 " clocks"
Kim Phillipsd82b0772007-04-30 15:26:21 -0500602);
Mario Six7cab1472018-08-06 10:23:36 +0200603
604#endif