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Rick Chenbaaa0622018-11-13 16:33:29 +08001/dts-v1/;
2
Bin Meng6b977a42021-05-10 20:23:40 +08003#include "binman.dtsi"
4
Rick Chenbaaa0622018-11-13 16:33:29 +08005/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "andestech,a25";
9 model = "andestech,a25";
10
11 aliases {
12 uart0 = &serial0;
13 spi0 = &spi;
14 };
15
16 chosen {
17 bootargs = "console=ttyS0,38400n8 debug loglevel=7";
18 stdout-path = "uart0:38400n8";
19 };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 timebase-frequency = <60000000>;
25 CPU0: cpu@0 {
26 device_type = "cpu";
27 reg = <0>;
28 status = "okay";
29 compatible = "riscv";
30 riscv,isa = "rv32imafdc";
Rick Chen5e56cda2019-04-02 15:56:43 +080031 riscv,priv-major = <1>;
32 riscv,priv-minor = <10>;
Rick Chenbaaa0622018-11-13 16:33:29 +080033 mmu-type = "riscv,sv32";
34 clock-frequency = <60000000>;
Rick Chen5e56cda2019-04-02 15:56:43 +080035 i-cache-size = <0x8000>;
36 i-cache-line-size = <32>;
Rick Chenbaaa0622018-11-13 16:33:29 +080037 d-cache-size = <0x8000>;
38 d-cache-line-size = <32>;
Rick Chen5e56cda2019-04-02 15:56:43 +080039 next-level-cache = <&L2>;
Rick Chenbaaa0622018-11-13 16:33:29 +080040 CPU0_intc: interrupt-controller {
41 #interrupt-cells = <1>;
42 interrupt-controller;
43 compatible = "riscv,cpu-intc";
44 };
45 };
Rick Chen5e56cda2019-04-02 15:56:43 +080046 CPU1: cpu@1 {
47 device_type = "cpu";
48 reg = <1>;
49 status = "okay";
50 compatible = "riscv";
51 riscv,isa = "rv32imafdc";
52 riscv,priv-major = <1>;
53 riscv,priv-minor = <10>;
54 mmu-type = "riscv,sv32";
55 clock-frequency = <60000000>;
56 i-cache-size = <0x8000>;
57 i-cache-line-size = <32>;
58 d-cache-size = <0x8000>;
59 d-cache-line-size = <32>;
60 next-level-cache = <&L2>;
61 CPU1_intc: interrupt-controller {
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 compatible = "riscv,cpu-intc";
65 };
66 };
Rick Chen3209fb82019-11-14 13:52:28 +080067 CPU2: cpu@2 {
68 device_type = "cpu";
69 reg = <2>;
70 status = "okay";
71 compatible = "riscv";
72 riscv,isa = "rv32imafdc";
73 riscv,priv-major = <1>;
74 riscv,priv-minor = <10>;
75 mmu-type = "riscv,sv32";
76 clock-frequency = <60000000>;
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <32>;
79 d-cache-size = <0x8000>;
80 d-cache-line-size = <32>;
81 next-level-cache = <&L2>;
82 CPU2_intc: interrupt-controller {
83 #interrupt-cells = <1>;
84 interrupt-controller;
85 compatible = "riscv,cpu-intc";
86 };
87 };
88 CPU3: cpu@3 {
89 device_type = "cpu";
90 reg = <3>;
91 status = "okay";
92 compatible = "riscv";
93 riscv,isa = "rv32imafdc";
94 riscv,priv-major = <1>;
95 riscv,priv-minor = <10>;
96 mmu-type = "riscv,sv32";
97 clock-frequency = <60000000>;
98 i-cache-size = <0x8000>;
99 i-cache-line-size = <32>;
100 d-cache-size = <0x8000>;
101 d-cache-line-size = <32>;
102 next-level-cache = <&L2>;
103 CPU3_intc: interrupt-controller {
104 #interrupt-cells = <1>;
105 interrupt-controller;
106 compatible = "riscv,cpu-intc";
107 };
108 };
Rick Chen5ff8f412019-08-28 18:46:10 +0800109 };
Rick Chen5e56cda2019-04-02 15:56:43 +0800110
Rick Chen5ff8f412019-08-28 18:46:10 +0800111 L2: l2-cache@e0500000 {
112 compatible = "v5l2cache";
113 cache-level = <2>;
114 cache-size = <0x40000>;
115 reg = <0xe0500000 0x40000>;
116 andes,inst-prefetch = <3>;
117 andes,data-prefetch = <3>;
118 /* The value format is <XRAMOCTL XRAMICTL> */
119 andes,tag-ram-ctl = <0 0>;
120 andes,data-ram-ctl = <0 0>;
Rick Chenbaaa0622018-11-13 16:33:29 +0800121 };
122
123 memory@0 {
124 device_type = "memory";
125 reg = <0x00000000 0x40000000>;
126 };
127
128 soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
Rick Chen5e56cda2019-04-02 15:56:43 +0800131 compatible = "simple-bus";
Rick Chenbaaa0622018-11-13 16:33:29 +0800132 ranges;
133
Rick Chen5e56cda2019-04-02 15:56:43 +0800134 plic0: interrupt-controller@e4000000 {
135 compatible = "riscv,plic0";
136 #address-cells = <1>;
137 #interrupt-cells = <1>;
138 interrupt-controller;
139 reg = <0xe4000000 0x2000000>;
140 riscv,ndev=<71>;
Rick Chen3209fb82019-11-14 13:52:28 +0800141 interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
142 &CPU1_intc 11 &CPU1_intc 9
143 &CPU2_intc 11 &CPU2_intc 9
144 &CPU3_intc 11 &CPU3_intc 9>;
Rick Chen5e56cda2019-04-02 15:56:43 +0800145 };
Rick Chenbaaa0622018-11-13 16:33:29 +0800146
Rick Chen5e56cda2019-04-02 15:56:43 +0800147 plic1: interrupt-controller@e6400000 {
148 compatible = "riscv,plic1";
149 #address-cells = <1>;
150 #interrupt-cells = <1>;
151 interrupt-controller;
152 reg = <0xe6400000 0x400000>;
153 riscv,ndev=<2>;
Rick Chen3209fb82019-11-14 13:52:28 +0800154 interrupts-extended = <&CPU0_intc 3
155 &CPU1_intc 3
156 &CPU2_intc 3
157 &CPU3_intc 3>;
Rick Chen5e56cda2019-04-02 15:56:43 +0800158 };
Rick Chenbaaa0622018-11-13 16:33:29 +0800159
Rick Chen5e56cda2019-04-02 15:56:43 +0800160 plmt0@e6000000 {
161 compatible = "riscv,plmt0";
Rick Chen3209fb82019-11-14 13:52:28 +0800162 interrupts-extended = <&CPU0_intc 7
163 &CPU1_intc 7
164 &CPU2_intc 7
165 &CPU3_intc 7>;
Rick Chenbaaa0622018-11-13 16:33:29 +0800166 reg = <0xe6000000 0x100000>;
167 };
168 };
169
170 spiclk: virt_100mhz {
171 #clock-cells = <0>;
172 compatible = "fixed-clock";
173 clock-frequency = <100000000>;
174 };
175
176 timer0: timer@f0400000 {
177 compatible = "andestech,atcpit100";
178 reg = <0xf0400000 0x1000>;
179 clock-frequency = <60000000>;
180 interrupts = <3 4>;
181 interrupt-parent = <&plic0>;
182 };
183
184 serial0: serial@f0300000 {
185 compatible = "andestech,uart16550", "ns16550a";
186 reg = <0xf0300000 0x1000>;
187 interrupts = <9 4>;
188 clock-frequency = <19660800>;
189 reg-shift = <2>;
190 reg-offset = <32>;
191 no-loopback-test = <1>;
192 interrupt-parent = <&plic0>;
193 };
194
195 mac0: mac@e0100000 {
196 compatible = "andestech,atmac100";
197 reg = <0xe0100000 0x1000>;
198 interrupts = <19 4>;
199 interrupt-parent = <&plic0>;
200 };
201
202 mmc0: mmc@f0e00000 {
203 compatible = "andestech,atfsdc010";
204 max-frequency = <100000000>;
205 clock-freq-min-max = <400000 100000000>;
206 fifo-depth = <0x10>;
207 reg = <0xf0e00000 0x1000>;
208 interrupts = <18 4>;
209 cap-sd-highspeed;
210 interrupt-parent = <&plic0>;
211 };
212
213 dma0: dma@f0c00000 {
214 compatible = "andestech,atcdmac300";
215 reg = <0xf0c00000 0x1000>;
216 interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
217 dma-channels = <8>;
218 interrupt-parent = <&plic0>;
219 };
220
221 lcd0: lcd@e0200000 {
222 compatible = "andestech,atflcdc100";
223 reg = <0xe0200000 0x1000>;
224 interrupts = <20 4>;
225 interrupt-parent = <&plic0>;
226 };
227
228 smc0: smc@e0400000 {
229 compatible = "andestech,atfsmc020";
230 reg = <0xe0400000 0x1000>;
231 };
232
233 snd0: snd@f0d00000 {
234 compatible = "andestech,atfac97";
235 reg = <0xf0d00000 0x1000>;
236 interrupts = <17 4>;
237 interrupt-parent = <&plic0>;
238 };
239
Rick Chen5e56cda2019-04-02 15:56:43 +0800240 pmu {
241 compatible = "riscv,base-pmu";
242 };
243
Rick Chenbaaa0622018-11-13 16:33:29 +0800244 virtio_mmio@fe007000 {
245 interrupts = <0x17 0x4>;
246 interrupt-parent = <0x2>;
247 reg = <0xfe007000 0x1000>;
248 compatible = "virtio,mmio";
249 };
250
251 virtio_mmio@fe006000 {
252 interrupts = <0x16 0x4>;
253 interrupt-parent = <0x2>;
254 reg = <0xfe006000 0x1000>;
255 compatible = "virtio,mmio";
256 };
257
258 virtio_mmio@fe005000 {
259 interrupts = <0x15 0x4>;
260 interrupt-parent = <0x2>;
261 reg = <0xfe005000 0x1000>;
262 compatible = "virtio,mmio";
263 };
264
265 virtio_mmio@fe004000 {
266 interrupts = <0x14 0x4>;
267 interrupt-parent = <0x2>;
268 reg = <0xfe004000 0x1000>;
269 compatible = "virtio,mmio";
270 };
271
272 virtio_mmio@fe003000 {
273 interrupts = <0x13 0x4>;
274 interrupt-parent = <0x2>;
275 reg = <0xfe003000 0x1000>;
276 compatible = "virtio,mmio";
277 };
278
279 virtio_mmio@fe002000 {
280 interrupts = <0x12 0x4>;
281 interrupt-parent = <0x2>;
282 reg = <0xfe002000 0x1000>;
283 compatible = "virtio,mmio";
284 };
285
286 virtio_mmio@fe001000 {
287 interrupts = <0x11 0x4>;
288 interrupt-parent = <0x2>;
289 reg = <0xfe001000 0x1000>;
290 compatible = "virtio,mmio";
291 };
292
293 virtio_mmio@fe000000 {
294 interrupts = <0x10 0x4>;
295 interrupt-parent = <0x2>;
296 reg = <0xfe000000 0x1000>;
297 compatible = "virtio,mmio";
298 };
299
300 nor@0,0 {
Rick Chen314d3ef2019-11-14 13:52:29 +0800301 #address-cells = <1>;
302 #size-cells = <1>;
Rick Chenbaaa0622018-11-13 16:33:29 +0800303 compatible = "cfi-flash";
Rick Chen314d3ef2019-11-14 13:52:29 +0800304 reg = <0x88000000 0x4000000>;
Rick Chenbaaa0622018-11-13 16:33:29 +0800305 bank-width = <2>;
306 device-width = <1>;
307 };
308
309 spi: spi@f0b00000 {
310 compatible = "andestech,atcspi200";
311 reg = <0xf0b00000 0x1000>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 num-cs = <1>;
315 clocks = <&spiclk>;
316 interrupts = <4 4>;
317 interrupt-parent = <&plic0>;
318 flash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000319 compatible = "jedec,spi-nor";
Rick Chenbaaa0622018-11-13 16:33:29 +0800320 spi-max-frequency = <50000000>;
321 reg = <0>;
322 spi-cpol;
323 spi-cpha;
324 };
325 };
326};